r600g,radeonsi: don't skip the context flush if a fence should be returned

[mesa.git] / src / gallium / drivers / radeonsi / si_state.c

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index b012d0991c1623ed523338325b01fbd23c014c3f..ab9c4cc28342fa610b37f827be2908b6625a8a80 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -78,7 +78,7 @@ static uint32_t cik_num_banks(struct si_screen *sscreen, unsigned bpe, unsigned
        }
 }
 
-static unsigned cik_tile_split(unsigned tile_split)
+unsigned cik_tile_split(unsigned tile_split)
 {
        switch (tile_split) {
        case 64:
@@ -107,7 +107,7 @@ static unsigned cik_tile_split(unsigned tile_split)
        return tile_split;
 }
 
-static unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
+unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
 {
        switch (macro_tile_aspect) {
        default:
@@ -127,7 +127,7 @@ static unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
        return macro_tile_aspect;
 }
 
-static unsigned cik_bank_wh(unsigned bankwh)
+unsigned cik_bank_wh(unsigned bankwh)
 {
        switch (bankwh) {
        default:
@@ -147,7 +147,7 @@ static unsigned cik_bank_wh(unsigned bankwh)
        return bankwh;
 }
 
-static unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
+unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
 {
        if (sscreen->b.info.si_tile_mode_array_valid) {
                uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
@@ -1514,7 +1514,7 @@ boolean si_is_format_supported(struct pipe_screen *screen,
        return retval == usage;
 }
 
-static unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
+unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
 {
        unsigned tile_mode_index = 0;
 
@@ -1705,7 +1705,7 @@ static void si_init_depth_surface(struct si_context *sctx,
        unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
        uint32_t z_info, s_info, db_depth_info;
        uint64_t z_offs, s_offs;
-       uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl;
+       uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
 
        switch (sctx->framebuffer.state.zsbuf->texture->format) {
        case PIPE_FORMAT_S8_UINT_Z24_UNORM:
@@ -2208,9 +2208,11 @@ static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
        struct si_context *sctx = (struct si_context *)ctx;
        struct si_pipe_shader_selector *sel = state;
 
+       /* skip if supplied shader is one already in use */
        if (sctx->ps_shader == sel)
                return;
 
+       /* use dummy shader if supplied shader is corrupt */
        if (!sel || !sel->current)
                sel = sctx->dummy_pixel_shader;
 
@@ -2926,18 +2928,6 @@ static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
        return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
 }
 
-static boolean si_dma_copy(struct pipe_context *ctx,
-                          struct pipe_resource *dst,
-                          unsigned dst_level,
-                          unsigned dst_x, unsigned dst_y, unsigned dst_z,
-                          struct pipe_resource *src,
-                          unsigned src_level,
-                          const struct pipe_box *src_box)
-{
-       /* XXX implement this or share evergreen_dma_blit with r600g */
-       return FALSE;
-}
-
 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
 {
        /* XXX Turn this into a proper state. Right now the queries are
@@ -3064,7 +3054,6 @@ void si_init_config(struct si_context *sctx)
        si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, 0);
        si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT, 0);
 
-       si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
        si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
        if (sctx->b.chip_class == SI) {
                si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,