amd: assume HTILE is always rb/pipe_aligned, remove ac_surface.u.gfx9.htile

[mesa.git] / src / gallium / drivers / radeonsi / si_state.c

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 5fef04b3cb2cf02237d5bda74bc190c680e92ebf..b20a59de1a1b9f7e62b6cdad0ddf6468ab515de0 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2540,9 +2540,9 @@ static void si_init_depth_surface(struct si_context *sctx, struct si_surface *su
 
          surf->db_htile_data_base = (tex->buffer.gpu_address + tex->surface.htile_offset) >> 8;
          surf->db_htile_surface =
-            S_028ABC_FULL_CACHE(1) | S_028ABC_PIPE_ALIGNED(tex->surface.u.gfx9.htile.pipe_aligned);
+            S_028ABC_FULL_CACHE(1) | S_028ABC_PIPE_ALIGNED(1);
          if (sctx->chip_class == GFX9) {
-            surf->db_htile_surface |= S_028ABC_RB_ALIGNED(tex->surface.u.gfx9.htile.rb_aligned);
+            surf->db_htile_surface |= S_028ABC_RB_ALIGNED(1);
          }
       }
    } else {