radeonsi: don't flush and wait for CB after depth-only rendering

[mesa.git] / src / gallium / drivers / radeonsi / si_state.c

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index a0d790ac2a946780bc49aae6a5b4f2d6dd6a8a61..b236bed306542bafe612a0b6293693e57f098dd5 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2535,8 +2535,11 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
         * (after FMASK decompression). Shader write -> FB read transitions
         * cannot happen for MSAA textures, because MSAA shader images are
         * not supported.
+        *
+        * Only flush and wait for CB if there is actually a bound color buffer.
         */
-       if (sctx->framebuffer.nr_samples <= 1) {
+       if (sctx->framebuffer.nr_samples <= 1 &&
+           sctx->framebuffer.state.nr_cbufs) {
                sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
                                 SI_CONTEXT_INV_GLOBAL_L2 |
                                 SI_CONTEXT_FLUSH_AND_INV_CB;
@@ -4023,7 +4026,9 @@ static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
                                 SI_CONTEXT_WRITEBACK_GLOBAL_L2;
        }
 
-       if (flags & PIPE_BARRIER_INDIRECT_BUFFER)
+       /* Indirect buffers use TC L2 on GFX9, but not older hw. */
+       if (sctx->screen->b.chip_class <= VI &&
+           flags & PIPE_BARRIER_INDIRECT_BUFFER)
                sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
 }