#include "util/u_format.h"
#include "util/u_format_s3tc.h"
#include "util/u_memory.h"
+#include "util/u_pstipple.h"
static void si_init_atom(struct r600_atom *atom, struct r600_atom **list_elem,
void (*emit)(struct si_context *ctx, struct r600_atom *state),
{
struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
struct tgsi_shader_info *info = si_get_vs_info(sctx);
- struct si_shader *vs = si_get_vs_state(sctx);
unsigned window_space =
- vs->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
+ info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
unsigned clipdist_mask =
info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
rs->multisample_enable = state->multisample;
rs->clip_plane_enable = state->clip_plane_enable;
rs->line_stipple_enable = state->line_stipple_enable;
+ rs->poly_stipple_enable = state->poly_stipple_enable;
+ rs->line_smooth = state->line_smooth;
+ rs->poly_smooth = state->poly_smooth;
polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
state->fill_back != PIPE_POLYGON_MODE_FILL);
si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
- S_028A48_MSAA_ENABLE(state->multisample) |
+ S_028A48_MSAA_ENABLE(state->multisample ||
+ state->poly_smooth ||
+ state->line_smooth) |
S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
*/
static void si_update_dsa_stencil_ref(struct si_context *sctx)
{
- struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ struct si_pm4_state *pm4;
struct pipe_stencil_ref *ref = &sctx->stencil_ref;
- struct si_state_dsa *dsa = sctx->queued.named.dsa;
+ struct si_state_dsa *dsa = sctx->queued.named.dsa;
- if (pm4 == NULL)
- return;
+ if (!dsa)
+ return;
+
+ pm4 = CALLOC_STRUCT(si_pm4_state);
+ if (pm4 == NULL)
+ return;
si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
S_028430_STENCILTESTVAL(ref->ref_value[0]) |
r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, 0);
}
- db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
- S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
+ db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
sctx->ps_db_shader_control;
+ /* Bug workaround for smoothing (overrasterization) on SI. */
+ if (sctx->b.chip_class == SI && sctx->smoothing_enabled)
+ db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
+ else
+ db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
+
/* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
SI_DRIVER_STATE_CONST_BUF, &constbuf);
+
+ /* Smoothing (only possible with nr_samples == 1) uses the same
+ * sample locations as the MSAA it simulates.
+ *
+ * Therefore, don't update the sample locations when
+ * transitioning from no AA to smoothing-equivalent AA, and
+ * vice versa.
+ */
+ if ((sctx->framebuffer.nr_samples != 1 ||
+ old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) &&
+ (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES ||
+ old_nr_samples != 1))
+ sctx->msaa_sample_locs.dirty = true;
}
}
/* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
r600_write_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
+}
+
+static void si_emit_msaa_sample_locs(struct r600_common_context *rctx,
+ struct r600_atom *atom)
+{
+ struct si_context *sctx = (struct si_context *)rctx;
+ struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
+ unsigned nr_samples = sctx->framebuffer.nr_samples;
- cayman_emit_msaa_sample_locs(cs, sctx->framebuffer.nr_samples);
+ cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples :
+ SI_NUM_SMOOTH_AA_SAMPLES);
}
+const struct r600_atom si_atom_msaa_sample_locs = { si_emit_msaa_sample_locs, 18 }; /* number of CS dwords */
+
static void si_emit_msaa_config(struct r600_common_context *rctx, struct r600_atom *atom)
{
struct si_context *sctx = (struct si_context *)rctx;
struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
- sctx->ps_iter_samples);
+ sctx->ps_iter_samples,
+ sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0);
}
const struct r600_atom si_atom_msaa_config = { si_emit_msaa_config, 10 }; /* number of CS dwords */
static void si_set_polygon_stipple(struct pipe_context *ctx,
const struct pipe_poly_stipple *state)
{
+ struct si_context *sctx = (struct si_context *)ctx;
+ struct pipe_resource *tex;
+ struct pipe_sampler_view *view;
+ bool is_zero = true;
+ bool is_one = true;
+ int i;
+
+ /* The hardware obeys 0 and 1 swizzles in the descriptor even if
+ * the resource is NULL/invalid. Take advantage of this fact and skip
+ * texture allocation if the stipple pattern is constant.
+ *
+ * This is an optimization for the common case when stippling isn't
+ * used but set_polygon_stipple is still called by st/mesa.
+ */
+ for (i = 0; i < Elements(state->stipple); i++) {
+ is_zero = is_zero && state->stipple[i] == 0;
+ is_one = is_one && state->stipple[i] == 0xffffffff;
+ }
+
+ if (is_zero || is_one) {
+ struct pipe_sampler_view templ = {{0}};
+
+ templ.swizzle_r = PIPE_SWIZZLE_ZERO;
+ templ.swizzle_g = PIPE_SWIZZLE_ZERO;
+ templ.swizzle_b = PIPE_SWIZZLE_ZERO;
+ /* The pattern should be inverted in the texture. */
+ templ.swizzle_a = is_zero ? PIPE_SWIZZLE_ONE : PIPE_SWIZZLE_ZERO;
+
+ view = ctx->create_sampler_view(ctx, NULL, &templ);
+ } else {
+ /* Create a new texture. */
+ tex = util_pstipple_create_stipple_texture(ctx, state->stipple);
+ if (!tex)
+ return;
+
+ view = util_pstipple_create_sampler_view(ctx, tex);
+ pipe_resource_reference(&tex, NULL);
+ }
+
+ ctx->set_sampler_views(ctx, PIPE_SHADER_FRAGMENT,
+ SI_POLY_STIPPLE_SAMPLER, 1, &view);
+ pipe_sampler_view_reference(&view, NULL);
+
+ /* Bind the sampler state if needed. */
+ if (!sctx->pstipple_sampler_state) {
+ sctx->pstipple_sampler_state = util_pstipple_create_sampler(ctx);
+ ctx->bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT,
+ SI_POLY_STIPPLE_SAMPLER, 1,
+ &sctx->pstipple_sampler_state);
+ }
}
static void si_texture_barrier(struct pipe_context *ctx)
si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT, 0);
si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
- si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
+ si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0);
si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
if (sctx->b.chip_class < CIK)
si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
switch (sctx->screen->b.family) {
case CHIP_BONAIRE:
si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
- si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
+ si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0);
break;
case CHIP_HAWAII:
si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x3a00161a);
case CHIP_MULLINS:
/* XXX todo */
default:
- si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
- si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
+ si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0);
+ si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0);
break;
}
} else {
raster_config = 0x00000082;
break;
case CHIP_HAINAN:
- raster_config = 0x00000000;
+ raster_config = 0;
break;
default:
fprintf(stderr,
"radeonsi: Unknown GPU, using 0 for raster_config\n");
- raster_config = 0x00000000;
+ raster_config = 0;
break;
}
si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
- si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
- si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
- si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
- si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
- si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
- si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
- si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
- si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
- si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
- si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
+ /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
+ si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
+ si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0);
+ si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, fui(1.0));
+ si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
+ si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, fui(1.0));
+ si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, fui(1.0));
+ si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, fui(1.0));
+ si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, fui(1.0));
+ si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0);
+ si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0);
+ si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0);
si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
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