radeonsi: pass alpha_ref value to PS in the user sgpr

[mesa.git] / src / gallium / drivers / radeonsi / si_state.c

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index adbb716fead76725733b6abceb9d7e9de881e27b..da7c3d0ab0c4798b86509c07606f3613c6133871 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -744,6 +744,9 @@ static void *si_create_dsa_state(struct pipe_context *ctx,
        if (state->alpha.enabled) {
                dsa->alpha_func = state->alpha.func;
                dsa->alpha_ref = state->alpha.ref_value;
+
+               si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
+                              SI_SGPR_ALPHA_REF * 4, fui(dsa->alpha_ref));
        } else {
                dsa->alpha_func = PIPE_FUNC_ALWAYS;
        }
@@ -2116,10 +2119,6 @@ static INLINE void si_shader_selector_key(struct pipe_context *ctx,
                            rctx->framebuffer.cbufs[0] &&
                            util_format_is_pure_integer(rctx->framebuffer.cbufs[0]->texture->format))
                                key->ps.alpha_func = PIPE_FUNC_ALWAYS;
-
-                       if (key->ps.alpha_func != PIPE_FUNC_ALWAYS &&
-                           key->ps.alpha_func != PIPE_FUNC_NEVER)
-                               key->ps.alpha_ref = rctx->queued.named.dsa->alpha_ref;
                } else {
                        key->ps.alpha_func = PIPE_FUNC_ALWAYS;
                }
@@ -3084,10 +3083,12 @@ void si_init_config(struct r600_context *rctx)
        si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
        si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
        si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
-       si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
-                      S_028AA8_SWITCH_ON_EOP(1) |
-                      S_028AA8_PARTIAL_VS_WAVE_ON(1) |
-                      S_028AA8_PRIMGROUP_SIZE(63));
+       if (rctx->b.chip_class == SI) {
+               si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
+                              S_028AA8_SWITCH_ON_EOP(1) |
+                              S_028AA8_PARTIAL_VS_WAVE_ON(1) |
+                              S_028AA8_PRIMGROUP_SIZE(63));
+       }
        si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
        si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
        if (rctx->b.chip_class < CIK)