radeonsi: Don't modify PA_SC_RASTER_CONFIG register value if rb_mask == 0
[mesa.git] / src / gallium / drivers / radeonsi / si_state.h
index 9acda3f5f146e03de8c127883eeb36b0d93391ff..0e067670c17f82dcba1285e743f2041425931373 100644 (file)
 #define SI_STATE_H
 
 #include "si_pm4.h"
-#include "../radeon/r600_pipe_common.h"
+#include "radeon/r600_pipe_common.h"
+
+struct si_screen;
+struct si_shader;
 
 struct si_state_blend {
        struct si_pm4_state     pm4;
@@ -36,6 +39,16 @@ struct si_state_blend {
        bool                    alpha_to_one;
 };
 
+struct si_state_sample_mask {
+       struct si_pm4_state     pm4;
+       uint16_t                sample_mask;
+};
+
+struct si_state_scissor {
+       struct si_pm4_state             pm4;
+       struct pipe_scissor_state       scissor;
+};
+
 struct si_state_viewport {
        struct si_pm4_state             pm4;
        struct pipe_viewport_state      viewport;
@@ -61,7 +74,6 @@ struct si_state_dsa {
        struct si_pm4_state     pm4;
        float                   alpha_ref;
        unsigned                alpha_func;
-       unsigned                db_render_control;
        uint8_t                 valuemask[2];
        uint8_t                 writemask[2];
 };
@@ -70,6 +82,7 @@ struct si_vertex_element
 {
        unsigned                        count;
        uint32_t                        rsrc_word3[PIPE_MAX_ATTRIBS];
+       uint32_t                        format_size[PIPE_MAX_ATTRIBS];
        struct pipe_vertex_element      elements[PIPE_MAX_ATTRIBS];
 };
 
@@ -79,43 +92,55 @@ union si_state {
                struct si_state_blend           *blend;
                struct si_pm4_state             *blend_color;
                struct si_pm4_state             *clip;
-               struct si_pm4_state             *sample_mask;
-               struct si_pm4_state             *scissor;
+               struct si_state_sample_mask     *sample_mask;
+               struct si_state_scissor         *scissor;
                struct si_state_viewport        *viewport;
-               struct si_pm4_state             *framebuffer;
                struct si_state_rasterizer      *rasterizer;
                struct si_state_dsa             *dsa;
                struct si_pm4_state             *fb_rs;
                struct si_pm4_state             *fb_blend;
                struct si_pm4_state             *dsa_stencil_ref;
+               struct si_pm4_state             *ta_bordercolor_base;
                struct si_pm4_state             *es;
                struct si_pm4_state             *gs;
                struct si_pm4_state             *gs_rings;
-               struct si_pm4_state             *gs_sampler;
                struct si_pm4_state             *gs_onoff;
                struct si_pm4_state             *vs;
-               struct si_pm4_state             *vs_sampler;
                struct si_pm4_state             *ps;
-               struct si_pm4_state             *ps_sampler;
                struct si_pm4_state             *spi;
-               struct si_pm4_state             *vertex_buffers;
-               struct si_pm4_state             *draw_info;
-               struct si_pm4_state             *draw;
        } named;
        struct si_pm4_state     *array[0];
 };
 
-#define NUM_TEX_UNITS 16
+#define SI_NUM_USER_SAMPLERS 16 /* AKA OpenGL textures units per shader */
 
 /* User sampler views:   0..15
  * FMASK sampler views: 16..31 (no sampler states)
  */
-#define FMASK_TEX_OFFSET       NUM_TEX_UNITS
-#define NUM_SAMPLER_VIEWS      (FMASK_TEX_OFFSET+NUM_TEX_UNITS)
-#define NUM_SAMPLER_STATES     NUM_TEX_UNITS
+#define SI_FMASK_TEX_OFFSET            SI_NUM_USER_SAMPLERS
+#define SI_NUM_SAMPLER_VIEWS           (SI_FMASK_TEX_OFFSET + SI_NUM_USER_SAMPLERS)
+#define SI_NUM_SAMPLER_STATES          SI_NUM_USER_SAMPLERS
+
+/* User constant buffers:   0..15
+ * Driver state constants:  16
+ */
+#define SI_NUM_USER_CONST_BUFFERS      16
+#define SI_DRIVER_STATE_CONST_BUF      SI_NUM_USER_CONST_BUFFERS
+#define SI_NUM_CONST_BUFFERS           (SI_DRIVER_STATE_CONST_BUF + 1)
+
+/* Read-write buffer slots.
+ *
+ * Ring buffers:        0..1
+ * Streamout buffers:   2..5
+ */
+#define SI_RING_ESGS           0
+#define SI_RING_GSVS           1
+#define SI_NUM_RING_BUFFERS    2
+#define SI_SO_BUF_OFFSET       SI_NUM_RING_BUFFERS
+#define SI_NUM_RW_BUFFERS      (SI_SO_BUF_OFFSET + 4)
+
+#define SI_NUM_VERTEX_BUFFERS  16
 
-#define NUM_PIPE_CONST_BUFFERS 16
-#define NUM_CONST_BUFFERS 19
 
 /* This represents resource descriptors in memory, such as buffer resources,
  * image resources, and sampler states.
@@ -130,6 +155,7 @@ struct si_descriptors {
 
        /* The buffer where resource descriptors are stored. */
        struct r600_resource *buffer;
+       unsigned buffer_offset;
 
        /* The i-th bit is set if that element is dirty (changed but not emitted). */
        unsigned dirty_mask;
@@ -151,14 +177,21 @@ struct si_descriptors {
 
 struct si_sampler_views {
        struct si_descriptors           desc;
-       struct pipe_sampler_view        *views[NUM_SAMPLER_VIEWS];
-       uint32_t                        *desc_data[NUM_SAMPLER_VIEWS];
+       struct pipe_sampler_view        *views[SI_NUM_SAMPLER_VIEWS];
+       uint32_t                        *desc_data[SI_NUM_SAMPLER_VIEWS];
+};
+
+struct si_sampler_states {
+       struct si_descriptors           desc;
+       uint32_t                        *desc_data[SI_NUM_SAMPLER_STATES];
+       void                            *saved_states[2]; /* saved for u_blitter */
 };
 
 struct si_buffer_resources {
        struct si_descriptors           desc;
        unsigned                        num_buffers;
        enum radeon_bo_usage            shader_usage; /* READ, WRITE, or READWRITE */
+       enum radeon_bo_priority         priority;
        struct pipe_resource            **buffers; /* this has num_buffers elements */
        uint32_t                        *desc_storage; /* this has num_buffers*4 elements */
        uint32_t                        **desc_data; /* an array of pointers pointing to desc_storage */
@@ -195,11 +228,11 @@ struct si_buffer_resources {
        } while(0)
 
 /* si_descriptors.c */
-void si_set_sampler_view(struct si_context *sctx, unsigned shader,
-                        unsigned slot, struct pipe_sampler_view *view,
-                        unsigned *view_desc);
+void si_set_sampler_descriptors(struct si_context *sctx, unsigned shader,
+                               unsigned start, unsigned count, void **states);
+void si_update_vertex_buffers(struct si_context *sctx);
 void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
-                       struct pipe_constant_buffer *input,
+                       struct pipe_resource *buffer,
                        unsigned stride, unsigned num_records,
                        bool add_tid, bool swizzle,
                        unsigned element_size, unsigned index_stride);
@@ -213,32 +246,33 @@ void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuf
                            const uint8_t *ptr, unsigned size, uint32_t *const_offset);
 
 /* si_state.c */
-struct si_pipe_shader_selector;
-struct si_surface;
+struct si_shader_selector;
 
 boolean si_is_format_supported(struct pipe_screen *screen,
                                enum pipe_format format,
                                enum pipe_texture_target target,
                                unsigned sample_count,
                                unsigned usage);
-int si_shader_select(struct pipe_context *ctx,
-                    struct si_pipe_shader_selector *sel,
-                    unsigned *dirty);
 void si_init_state_functions(struct si_context *sctx);
 void si_init_config(struct si_context *sctx);
+unsigned cik_bank_wh(unsigned bankwh);
+unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode);
+unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect);
+unsigned cik_tile_split(unsigned tile_split);
+uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex);
+unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil);
+
+/* si_state_shader.c */
+void si_update_shaders(struct si_context *sctx);
+void si_init_shader_functions(struct si_context *sctx);
 
 /* si_state_draw.c */
 extern const struct r600_atom si_atom_cache_flush;
+extern const struct r600_atom si_atom_msaa_config;
 void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *atom);
 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
 
 /* si_commands.c */
 void si_cmd_context_control(struct si_pm4_state *pm4);
-void si_cmd_draw_index_2(struct si_pm4_state *pm4, uint32_t max_size,
-                        uint64_t index_base, uint32_t index_count,
-                        uint32_t initiator, bool predicate);
-void si_cmd_draw_index_auto(struct si_pm4_state *pm4, uint32_t count,
-                           uint32_t initiator, bool predicate);
-void si_cmd_surface_sync(struct si_pm4_state *pm4, uint32_t cp_coher_cntl);
 
 #endif