radeonsi: Don't modify PA_SC_RASTER_CONFIG register value if rb_mask == 0

[mesa.git] / src / gallium / drivers / radeonsi / si_state.h

diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index ae42e6673b58b7b7b71cea25d00f4c88742a809c..0e067670c17f82dcba1285e743f2041425931373 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -28,9 +28,10 @@
 #define SI_STATE_H
 
 #include "si_pm4.h"
-#include "../radeon/r600_pipe_common.h"
+#include "radeon/r600_pipe_common.h"
 
 struct si_screen;
+struct si_shader;
 
 struct si_state_blend {
        struct si_pm4_state     pm4;
@@ -38,6 +39,16 @@ struct si_state_blend {
        bool                    alpha_to_one;
 };
 
+struct si_state_sample_mask {
+       struct si_pm4_state     pm4;
+       uint16_t                sample_mask;
+};
+
+struct si_state_scissor {
+       struct si_pm4_state             pm4;
+       struct pipe_scissor_state       scissor;
+};
+
 struct si_state_viewport {
        struct si_pm4_state             pm4;
        struct pipe_viewport_state      viewport;
@@ -63,7 +74,6 @@ struct si_state_dsa {
        struct si_pm4_state     pm4;
        float                   alpha_ref;
        unsigned                alpha_func;
-       unsigned                db_render_control;
        uint8_t                 valuemask[2];
        uint8_t                 writemask[2];
 };
@@ -72,6 +82,7 @@ struct si_vertex_element
 {
        unsigned                        count;
        uint32_t                        rsrc_word3[PIPE_MAX_ATTRIBS];
+       uint32_t                        format_size[PIPE_MAX_ATTRIBS];
        struct pipe_vertex_element      elements[PIPE_MAX_ATTRIBS];
 };
 
@@ -81,27 +92,22 @@ union si_state {
                struct si_state_blend           *blend;
                struct si_pm4_state             *blend_color;
                struct si_pm4_state             *clip;
-               struct si_pm4_state             *sample_mask;
-               struct si_pm4_state             *scissor;
+               struct si_state_sample_mask     *sample_mask;
+               struct si_state_scissor         *scissor;
                struct si_state_viewport        *viewport;
                struct si_state_rasterizer      *rasterizer;
                struct si_state_dsa             *dsa;
                struct si_pm4_state             *fb_rs;
                struct si_pm4_state             *fb_blend;
                struct si_pm4_state             *dsa_stencil_ref;
+               struct si_pm4_state             *ta_bordercolor_base;
                struct si_pm4_state             *es;
                struct si_pm4_state             *gs;
                struct si_pm4_state             *gs_rings;
-               struct si_pm4_state             *gs_sampler;
                struct si_pm4_state             *gs_onoff;
                struct si_pm4_state             *vs;
-               struct si_pm4_state             *vs_sampler;
                struct si_pm4_state             *ps;
-               struct si_pm4_state             *ps_sampler;
                struct si_pm4_state             *spi;
-               struct si_pm4_state             *vertex_buffers;
-               struct si_pm4_state             *draw_info;
-               struct si_pm4_state             *draw;
        } named;
        struct si_pm4_state     *array[0];
 };
@@ -149,6 +155,7 @@ struct si_descriptors {
 
        /* The buffer where resource descriptors are stored. */
        struct r600_resource *buffer;
+       unsigned buffer_offset;
 
        /* The i-th bit is set if that element is dirty (changed but not emitted). */
        unsigned dirty_mask;
@@ -174,6 +181,12 @@ struct si_sampler_views {
        uint32_t                        *desc_data[SI_NUM_SAMPLER_VIEWS];
 };
 
+struct si_sampler_states {
+       struct si_descriptors           desc;
+       uint32_t                        *desc_data[SI_NUM_SAMPLER_STATES];
+       void                            *saved_states[2]; /* saved for u_blitter */
+};
+
 struct si_buffer_resources {
        struct si_descriptors           desc;
        unsigned                        num_buffers;
@@ -215,11 +228,11 @@ struct si_buffer_resources {
        } while(0)
 
 /* si_descriptors.c */
-void si_set_sampler_view(struct si_context *sctx, unsigned shader,
-                        unsigned slot, struct pipe_sampler_view *view,
-                        unsigned *view_desc);
+void si_set_sampler_descriptors(struct si_context *sctx, unsigned shader,
+                               unsigned start, unsigned count, void **states);
+void si_update_vertex_buffers(struct si_context *sctx);
 void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
-                       struct pipe_constant_buffer *input,
+                       struct pipe_resource *buffer,
                        unsigned stride, unsigned num_records,
                        bool add_tid, bool swizzle,
                        unsigned element_size, unsigned index_stride);
@@ -233,25 +246,26 @@ void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuf
                            const uint8_t *ptr, unsigned size, uint32_t *const_offset);
 
 /* si_state.c */
-struct si_pipe_shader_selector;
+struct si_shader_selector;
 
 boolean si_is_format_supported(struct pipe_screen *screen,
                                enum pipe_format format,
                                enum pipe_texture_target target,
                                unsigned sample_count,
                                unsigned usage);
-int si_shader_select(struct pipe_context *ctx,
-                    struct si_pipe_shader_selector *sel);
 void si_init_state_functions(struct si_context *sctx);
 void si_init_config(struct si_context *sctx);
 unsigned cik_bank_wh(unsigned bankwh);
 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode);
 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect);
 unsigned cik_tile_split(unsigned tile_split);
-uint32_t si_num_banks(struct si_screen *sscreen, unsigned bpe, unsigned tile_split,
-                     unsigned tile_mode_index);
+uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex);
 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil);
 
+/* si_state_shader.c */
+void si_update_shaders(struct si_context *sctx);
+void si_init_shader_functions(struct si_context *sctx);
+
 /* si_state_draw.c */
 extern const struct r600_atom si_atom_cache_flush;
 extern const struct r600_atom si_atom_msaa_config;
@@ -260,18 +274,5 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
 
 /* si_commands.c */
 void si_cmd_context_control(struct si_pm4_state *pm4);
-void si_cmd_draw_index_2(struct si_pm4_state *pm4, uint32_t max_size,
-                        uint64_t index_base, uint32_t index_count,
-                        uint32_t initiator, bool predicate);
-void si_cmd_draw_index_auto(struct si_pm4_state *pm4, uint32_t count,
-                           uint32_t initiator, bool predicate);
-void si_cmd_draw_indirect(struct si_pm4_state *pm4, uint64_t indirect_va,
-                         uint32_t indirect_offset, uint32_t base_vtx_loc,
-                         uint32_t start_inst_loc, bool predicate);
-void si_cmd_draw_index_indirect(struct si_pm4_state *pm4, uint64_t indirect_va,
-                               uint64_t index_va, uint32_t index_max_size,
-                               uint32_t indirect_offset, uint32_t base_vtx_loc,
-                               uint32_t start_inst_loc, bool predicate);
-void si_cmd_surface_sync(struct si_pm4_state *pm4, uint32_t cp_coher_cntl);
 
 #endif