#include "si_pm4.h"
#include "radeon/r600_pipe_common.h"
-#define SI_NUM_SHADERS (PIPE_SHADER_TESS_EVAL+1)
+#define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_TESS_EVAL+1)
+#define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE+1)
+
+#define SI_MAX_ATTRIBS 16
+#define SI_NUM_VERTEX_BUFFERS SI_MAX_ATTRIBS
+#define SI_NUM_SAMPLERS 32 /* OpenGL textures units per shader */
+#define SI_NUM_CONST_BUFFERS 16
+#define SI_NUM_IMAGES 16
+#define SI_NUM_SHADER_BUFFERS 16
+
+#define SI_TESS_OFFCHIP_BLOCK_SIZE (8192 * 4)
struct si_screen;
struct si_shader;
struct si_state_blend {
struct si_pm4_state pm4;
uint32_t cb_target_mask;
+ bool alpha_to_coverage;
bool alpha_to_one;
-};
-
-struct si_state_sample_mask {
- struct si_pm4_state pm4;
- uint16_t sample_mask;
-};
-
-struct si_state_scissor {
- struct si_pm4_state pm4;
- struct pipe_scissor_state scissor;
-};
-
-struct si_state_viewport {
- struct si_pm4_state pm4;
- struct pipe_viewport_state viewport;
+ bool dual_src_blend;
+ /* Set 0xf or 0x0 (4 bits) per render target if the following is
+ * true. ANDed with spi_shader_col_format.
+ */
+ unsigned blend_enable_4bit;
+ unsigned need_src_alpha_4bit;
};
struct si_state_rasterizer {
struct si_pm4_state pm4;
+ /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */
+ struct si_pm4_state pm4_poly_offset[3];
bool flatshade;
bool two_side;
bool multisample_enable;
+ bool force_persample_interp;
bool line_stipple_enable;
unsigned sprite_coord_enable;
unsigned pa_sc_line_stipple;
unsigned pa_cl_clip_cntl;
unsigned clip_plane_enable;
- float offset_units;
- float offset_scale;
bool poly_stipple_enable;
bool line_smooth;
bool poly_smooth;
+ bool uses_poly_offset;
+ bool clamp_fragment_color;
+ bool rasterizer_discard;
+ bool scissor_enable;
};
-struct si_state_dsa {
- struct si_pm4_state pm4;
- unsigned alpha_func;
+struct si_dsa_stencil_ref_part {
uint8_t valuemask[2];
uint8_t writemask[2];
};
+struct si_state_dsa {
+ struct si_pm4_state pm4;
+ unsigned alpha_func;
+ struct si_dsa_stencil_ref_part stencil_ref;
+};
+
+struct si_stencil_ref {
+ struct r600_atom atom;
+ struct pipe_stencil_ref state;
+ struct si_dsa_stencil_ref_part dsa_part;
+};
+
struct si_vertex_element
{
unsigned count;
- uint32_t rsrc_word3[PIPE_MAX_ATTRIBS];
- uint32_t format_size[PIPE_MAX_ATTRIBS];
- struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS];
+ uint32_t rsrc_word3[SI_MAX_ATTRIBS];
+ uint32_t format_size[SI_MAX_ATTRIBS];
+ struct pipe_vertex_element elements[SI_MAX_ATTRIBS];
};
union si_state {
struct {
struct si_state_blend *blend;
- struct si_pm4_state *blend_color;
- struct si_pm4_state *clip;
- struct si_state_sample_mask *sample_mask;
- struct si_state_scissor *scissor[16];
- struct si_state_viewport *viewport[16];
struct si_state_rasterizer *rasterizer;
struct si_state_dsa *dsa;
- struct si_pm4_state *fb_rs;
- struct si_pm4_state *fb_blend;
- struct si_pm4_state *dsa_stencil_ref;
- struct si_pm4_state *ta_bordercolor_base;
+ struct si_pm4_state *poly_offset;
+ struct si_pm4_state *ls;
+ struct si_pm4_state *hs;
struct si_pm4_state *es;
struct si_pm4_state *gs;
- struct si_pm4_state *gs_rings;
- struct si_pm4_state *gs_onoff;
+ struct si_pm4_state *vgt_shader_config;
struct si_pm4_state *vs;
struct si_pm4_state *ps;
- struct si_pm4_state *spi;
} named;
struct si_pm4_state *array[0];
};
+union si_state_atoms {
+ struct {
+ /* The order matters. */
+ struct r600_atom *cache_flush;
+ struct r600_atom *render_cond;
+ struct r600_atom *streamout_begin;
+ struct r600_atom *streamout_enable; /* must be after streamout_begin */
+ struct r600_atom *framebuffer;
+ struct r600_atom *msaa_sample_locs;
+ struct r600_atom *db_render_state;
+ struct r600_atom *msaa_config;
+ struct r600_atom *sample_mask;
+ struct r600_atom *cb_render_state;
+ struct r600_atom *blend_color;
+ struct r600_atom *clip_regs;
+ struct r600_atom *clip_state;
+ struct r600_atom *shader_userdata;
+ struct r600_atom *scissors;
+ struct r600_atom *viewports;
+ struct r600_atom *stencil_ref;
+ struct r600_atom *spi_map;
+ } s;
+ struct r600_atom *array[0];
+};
+
+#define SI_NUM_ATOMS (sizeof(union si_state_atoms)/sizeof(struct r600_atom*))
+
struct si_shader_data {
struct r600_atom atom;
uint32_t sh_base[SI_NUM_SHADERS];
};
-#define SI_NUM_USER_SAMPLERS 16 /* AKA OpenGL textures units per shader */
-#define SI_POLY_STIPPLE_SAMPLER SI_NUM_USER_SAMPLERS
-#define SI_NUM_SAMPLERS (SI_POLY_STIPPLE_SAMPLER + 1)
+/* Private read-write buffer slots. */
+enum {
+ SI_HS_RING_TESS_FACTOR,
+ SI_HS_RING_TESS_OFFCHIP,
-/* User sampler views: 0..15
- * Polygon stipple tex: 16
- * FMASK sampler views: 17..33 (no sampler states)
- */
-#define SI_FMASK_TEX_OFFSET SI_NUM_SAMPLERS
-#define SI_NUM_SAMPLER_VIEWS (SI_FMASK_TEX_OFFSET + SI_NUM_SAMPLERS)
-#define SI_NUM_SAMPLER_STATES SI_NUM_SAMPLERS
+ SI_ES_RING_ESGS,
+ SI_GS_RING_ESGS,
-/* User constant buffers: 0..15
- * Driver state constants: 16
- */
-#define SI_NUM_USER_CONST_BUFFERS 16
-#define SI_DRIVER_STATE_CONST_BUF SI_NUM_USER_CONST_BUFFERS
-#define SI_NUM_CONST_BUFFERS (SI_DRIVER_STATE_CONST_BUF + 1)
+ SI_GS_RING_GSVS0,
+ SI_GS_RING_GSVS1,
+ SI_GS_RING_GSVS2,
+ SI_GS_RING_GSVS3,
+ SI_VS_RING_GSVS,
-/* Read-write buffer slots.
- *
- * Ring buffers: 0..1
- * Streamout buffers: 2..5
- */
-#define SI_RING_ESGS 0
-#define SI_RING_GSVS 1
-#define SI_NUM_RING_BUFFERS 2
-#define SI_SO_BUF_OFFSET SI_NUM_RING_BUFFERS
-#define SI_NUM_RW_BUFFERS (SI_SO_BUF_OFFSET + 4)
+ SI_VS_STREAMOUT_BUF0,
+ SI_VS_STREAMOUT_BUF1,
+ SI_VS_STREAMOUT_BUF2,
+ SI_VS_STREAMOUT_BUF3,
-#define SI_NUM_VERTEX_BUFFERS 16
+ SI_HS_CONST_DEFAULT_TESS_LEVELS,
+ SI_VS_CONST_CLIP_PLANES,
+ SI_PS_CONST_POLY_STIPPLE,
+ SI_PS_CONST_SAMPLE_POSITIONS,
+ SI_NUM_RW_BUFFERS,
+};
-/* This represents resource descriptors in memory, such as buffer resources,
+/* Indices into sctx->descriptors, laid out so that gfx and compute pipelines
+ * are contiguous:
+ *
+ * 0 - rw buffers
+ * 1 - vertex const buffers
+ * 2 - vertex shader buffers
+ * ...
+ * 5 - fragment const buffers
+ * ...
+ * 21 - compute const buffers
+ * ...
+ */
+#define SI_SHADER_DESCS_CONST_BUFFERS 0
+#define SI_SHADER_DESCS_SHADER_BUFFERS 1
+#define SI_SHADER_DESCS_SAMPLERS 2
+#define SI_SHADER_DESCS_IMAGES 3
+#define SI_NUM_SHADER_DESCS 4
+
+#define SI_DESCS_RW_BUFFERS 0
+#define SI_DESCS_FIRST_SHADER 1
+#define SI_DESCS_FIRST_COMPUTE (SI_DESCS_FIRST_SHADER + \
+ PIPE_SHADER_COMPUTE * SI_NUM_SHADER_DESCS)
+#define SI_NUM_DESCS (SI_DESCS_FIRST_SHADER + \
+ SI_NUM_SHADERS * SI_NUM_SHADER_DESCS)
+
+/* This represents descriptors in memory, such as buffer resources,
* image resources, and sampler states.
*/
struct si_descriptors {
- struct r600_atom atom;
-
- /* The size of one resource descriptor. */
+ /* The list of descriptors in malloc'd memory. */
+ uint32_t *list;
+ /* The size of one descriptor. */
unsigned element_dw_size;
- /* The maximum number of resource descriptors. */
+ /* The maximum number of descriptors. */
unsigned num_elements;
- /* The buffer where resource descriptors are stored. */
+ /* The buffer where the descriptors have been uploaded. */
struct r600_resource *buffer;
unsigned buffer_offset;
- /* The i-th bit is set if that element is dirty (changed but not emitted). */
- uint64_t dirty_mask;
- /* The i-th bit is set if that element is enabled (non-NULL resource). */
- uint64_t enabled_mask;
+ /* Offset in CE RAM */
+ unsigned ce_offset;
+
+ /* elements of the list that are changed and need to be uploaded */
+ unsigned dirty_mask;
- /* We can't update descriptors directly because the GPU might be
- * reading them at the same time, so we have to update them
- * in a copy-on-write manner. Each such copy is called a context,
- * which is just another array descriptors in the same buffer. */
- unsigned current_context_id;
- /* The size of a context, should be equal to 4*element_dw_size*num_elements. */
- unsigned context_size;
+ /* Whether the CE ram is dirty and needs to be reinitialized entirely
+ * before we can do partial updates. */
+ bool ce_ram_dirty;
/* The shader userdata offset within a shader where the 64-bit pointer to the descriptor
* array will be stored. */
unsigned shader_userdata_offset;
+ /* Whether the pointer should be re-emitted. */
bool pointer_dirty;
};
struct si_sampler_views {
- struct si_descriptors desc;
- struct pipe_sampler_view *views[SI_NUM_SAMPLER_VIEWS];
- uint32_t *desc_data[SI_NUM_SAMPLER_VIEWS];
-};
+ struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
+ void *sampler_states[SI_NUM_SAMPLERS];
-struct si_sampler_states {
- struct si_descriptors desc;
- uint32_t *desc_data[SI_NUM_SAMPLER_STATES];
- void *saved_states[2]; /* saved for u_blitter */
+ /* The i-th bit is set if that element is enabled (non-NULL resource). */
+ unsigned enabled_mask;
};
struct si_buffer_resources {
- struct si_descriptors desc;
- unsigned num_buffers;
enum radeon_bo_usage shader_usage; /* READ, WRITE, or READWRITE */
enum radeon_bo_priority priority;
struct pipe_resource **buffers; /* this has num_buffers elements */
- uint32_t *desc_storage; /* this has num_buffers*4 elements */
- uint32_t **desc_data; /* an array of pointers pointing to desc_storage */
+
+ /* The i-th bit is set if that element is enabled (non-NULL resource). */
+ unsigned enabled_mask;
};
#define si_pm4_block_idx(member) \
si_pm4_block_idx(member)); \
} while(0)
-#define si_pm4_set_state(sctx, member, value) \
- do { \
- if ((sctx)->queued.named.member != (value)) { \
- si_pm4_free_state(sctx, \
- (struct si_pm4_state *)(sctx)->queued.named.member, \
- si_pm4_block_idx(member)); \
- (sctx)->queued.named.member = (value); \
- } \
- } while(0)
-
/* si_descriptors.c */
-void si_set_sampler_descriptors(struct si_context *sctx, unsigned shader,
- unsigned start, unsigned count, void **states);
-void si_update_vertex_buffers(struct si_context *sctx);
-void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
+void si_ce_reinitialize_all_descriptors(struct si_context *sctx);
+void si_ce_enable_loads(struct radeon_winsys_cs *ib);
+void si_set_mutable_tex_desc_fields(struct r600_texture *tex,
+ const struct radeon_surf_level *base_level_info,
+ unsigned base_level, unsigned first_level,
+ unsigned block_width, bool is_stencil,
+ uint32_t *state);
+void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
struct pipe_resource *buffer,
unsigned stride, unsigned num_records,
bool add_tid, bool swizzle,
- unsigned element_size, unsigned index_stride);
+ unsigned element_size, unsigned index_stride, uint64_t offset);
void si_init_all_descriptors(struct si_context *sctx);
+bool si_upload_graphics_shader_descriptors(struct si_context *sctx);
+bool si_upload_compute_shader_descriptors(struct si_context *sctx);
void si_release_all_descriptors(struct si_context *sctx);
void si_all_descriptors_begin_new_cs(struct si_context *sctx);
-void si_copy_buffer(struct si_context *sctx,
- struct pipe_resource *dst, struct pipe_resource *src,
- uint64_t dst_offset, uint64_t src_offset, unsigned size, bool is_framebuffer);
void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuffer,
const uint8_t *ptr, unsigned size, uint32_t *const_offset);
+void si_update_all_texture_descriptors(struct si_context *sctx);
void si_shader_change_notify(struct si_context *sctx);
-
+void si_update_compressed_colortex_masks(struct si_context *sctx);
+void si_emit_graphics_shader_userdata(struct si_context *sctx,
+ struct r600_atom *atom);
+void si_emit_compute_shader_userdata(struct si_context *sctx);
+void si_set_rw_buffer(struct si_context *sctx,
+ uint slot, const struct pipe_constant_buffer *input);
/* si_state.c */
struct si_shader_selector;
-boolean si_is_format_supported(struct pipe_screen *screen,
- enum pipe_format format,
- enum pipe_texture_target target,
- unsigned sample_count,
- unsigned usage);
+void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
+ struct r600_atom **list_elem,
+ void (*emit_func)(struct si_context *ctx, struct r600_atom *state));
void si_init_state_functions(struct si_context *sctx);
-unsigned cik_bank_wh(unsigned bankwh);
-unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode);
-unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect);
-unsigned cik_tile_split(unsigned tile_split);
-unsigned si_array_mode(unsigned mode);
-uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex);
-unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil);
+void si_init_screen_state_functions(struct si_screen *sscreen);
+void
+si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
+ enum pipe_format format,
+ unsigned first_element, unsigned last_element,
+ uint32_t *state);
+void
+si_make_texture_descriptor(struct si_screen *screen,
+ struct r600_texture *tex,
+ bool sampler,
+ enum pipe_texture_target target,
+ enum pipe_format pipe_format,
+ const unsigned char state_swizzle[4],
+ unsigned first_level, unsigned last_level,
+ unsigned first_layer, unsigned last_layer,
+ unsigned width, unsigned height, unsigned depth,
+ uint32_t *state,
+ uint32_t *fmask_state);
struct pipe_sampler_view *
si_create_sampler_view_custom(struct pipe_context *ctx,
struct pipe_resource *texture,
const struct pipe_sampler_view *state,
unsigned width0, unsigned height0,
unsigned force_level);
+void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state);
/* si_state_shader.c */
-void si_update_shaders(struct si_context *sctx);
+bool si_update_shaders(struct si_context *sctx);
void si_init_shader_functions(struct si_context *sctx);
+bool si_init_shader_cache(struct si_screen *sscreen);
+void si_destroy_shader_cache(struct si_screen *sscreen);
/* si_state_draw.c */
-extern const struct r600_atom si_atom_cache_flush;
-extern const struct r600_atom si_atom_msaa_sample_locs;
-extern const struct r600_atom si_atom_msaa_config;
-void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom *atom);
+void si_emit_cache_flush(struct si_context *sctx, struct r600_atom *atom);
+void si_ce_pre_draw_synchronization(struct si_context *sctx);
+void si_ce_post_draw_synchronization(struct si_context *sctx);
void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
+void si_trace_emit(struct si_context *sctx);
-/* si_commands.c */
-void si_cmd_context_control(struct si_pm4_state *pm4);
+
+static inline unsigned
+si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
+{
+ if (stencil)
+ return rtex->surface.stencil_tiling_index[level];
+ else
+ return rtex->surface.tiling_index[level];
+}
#endif
projects / mesa.git / blobdiff