unsigned cull_back:1;
unsigned depth_clamp_any:1;
unsigned provoking_vertex_first:1;
+ unsigned polygon_mode_enabled:1;
+ unsigned polygon_mode_is_lines:1;
};
struct si_dsa_stencil_ref_part {
uint16_t first_vb_use_mask;
/* Vertex buffer descriptor list size aligned for optimal prefetch. */
- uint16_t desc_list_byte_size;
+ uint16_t vb_desc_list_alloc_size;
uint16_t instance_divisor_is_one; /* bitmask of inputs */
uint16_t instance_divisor_is_fetched; /* bitmask of inputs */
};
SI_TRACKED_PA_SC_CLIPRECT_RULE,
+ SI_TRACKED_PA_SC_LINE_STIPPLE,
+
SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
SI_TRACKED_VGT_GSVS_RING_OFFSET_1, /* 3 consecutive registers */
struct util_queue_fence *ready_fence,
struct si_compiler_ctx_state *compiler_ctx_state,
void *job, util_queue_execute_func execute);
-void si_get_active_slot_masks(const struct tgsi_shader_info *info,
+void si_get_active_slot_masks(const struct si_shader_info *info,
uint32_t *const_and_shader_buffers,
uint64_t *samplers_and_images);
int si_shader_select_with_key(struct si_screen *sscreen,