#define SI_NUM_SAMPLERS 32 /* OpenGL textures units per shader */
#define SI_NUM_CONST_BUFFERS 16
#define SI_NUM_IMAGES 16
+#define SI_NUM_IMAGE_SLOTS (SI_NUM_IMAGES * 2) /* the second half are FMASK slots */
#define SI_NUM_SHADER_BUFFERS 16
struct si_screen;
unsigned blend_enable_4bit;
unsigned need_src_alpha_4bit;
unsigned commutative_4bit;
+ unsigned dcc_msaa_corruption_4bit;
bool alpha_to_coverage:1;
bool alpha_to_one:1;
bool dual_src_blend:1;
unsigned clip_plane_enable:8;
unsigned half_pixel_center:1;
unsigned flatshade:1;
+ unsigned flatshade_first:1;
unsigned two_side:1;
unsigned multisample_enable:1;
unsigned force_persample_interp:1;
unsigned cull_back:1;
unsigned depth_clamp_any:1;
unsigned provoking_vertex_first:1;
+ unsigned polygon_mode_enabled:1;
+ unsigned polygon_mode_is_lines:1;
};
struct si_dsa_stencil_ref_part {
uint16_t first_vb_use_mask;
/* Vertex buffer descriptor list size aligned for optimal prefetch. */
- uint16_t desc_list_byte_size;
+ uint16_t vb_desc_list_alloc_size;
uint16_t instance_divisor_is_one; /* bitmask of inputs */
uint16_t instance_divisor_is_fetched; /* bitmask of inputs */
};
struct si_atom spi_map;
struct si_atom scratch_state;
struct si_atom window_rectangles;
+ struct si_atom shader_query;
} s;
struct si_atom array[0];
};
uint32_t sh_base[SI_NUM_SHADERS];
};
+#define SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK \
+ (S_02881C_USE_VTX_POINT_SIZE(1) | \
+ S_02881C_USE_VTX_EDGE_FLAG(1) | \
+ S_02881C_USE_VTX_RENDER_TARGET_INDX(1) | \
+ S_02881C_USE_VTX_VIEWPORT_INDX(1) | \
+ S_02881C_VS_OUT_MISC_VEC_ENA(1) | \
+ S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1))
+
/* The list of registers whose emitted values are remembered by si_context. */
enum si_tracked_reg {
SI_TRACKED_DB_RENDER_CONTROL, /* 2 consecutive registers */
SI_TRACKED_PA_SU_PRIM_FILTER_CNTL,
SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
- SI_TRACKED_PA_CL_VS_OUT_CNTL,
+ SI_TRACKED_PA_CL_VS_OUT_CNTL__VS, /* set with SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK*/
+ SI_TRACKED_PA_CL_VS_OUT_CNTL__CL, /* set with ~SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK */
SI_TRACKED_PA_CL_CLIP_CNTL,
SI_TRACKED_PA_SC_BINNER_CNTL_0,
SI_TRACKED_PA_SC_CLIPRECT_RULE,
+ SI_TRACKED_PA_SC_LINE_STIPPLE,
+
SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
- SI_TRACKED_VGT_GSVS_RING_OFFSET_1, /* 4 consecutive registers */
+ SI_TRACKED_VGT_GSVS_RING_OFFSET_1, /* 3 consecutive registers */
SI_TRACKED_VGT_GSVS_RING_OFFSET_2,
SI_TRACKED_VGT_GSVS_RING_OFFSET_3,
- SI_TRACKED_VGT_GS_OUT_PRIM_TYPE,
SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
SI_TRACKED_VGT_GS_MAX_VERT_OUT,
SI_TRACKED_VGT_PRIMITIVEID_EN,
SI_TRACKED_VGT_REUSE_OFF,
SI_TRACKED_SPI_VS_OUT_CONFIG,
- SI_TRACKED_SPI_SHADER_POS_FORMAT,
SI_TRACKED_PA_CL_VTE_CNTL,
+ SI_TRACKED_PA_CL_NGG_CNTL,
+ SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
+ SI_TRACKED_GE_NGG_SUBGRP_CNTL,
+
+ SI_TRACKED_SPI_SHADER_IDX_FORMAT, /* 2 consecutive registers */
+ SI_TRACKED_SPI_SHADER_POS_FORMAT,
SI_TRACKED_SPI_PS_INPUT_ENA, /* 2 consecutive registers */
SI_TRACKED_SPI_PS_INPUT_ADDR,
SI_PS_IMAGE_COLORBUF0_FMASK,
SI_PS_IMAGE_COLORBUF0_FMASK_HI,
+ GFX10_GS_QUERY_BUF,
+
SI_NUM_RW_BUFFERS,
};
void si_emit_dpbb_state(struct si_context *sctx);
/* si_state_shaders.c */
-void *si_get_ir_binary(struct si_shader_selector *sel);
-bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
+void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es,
+ unsigned char ir_sha1_cache_key[20]);
+bool si_shader_cache_load_shader(struct si_screen *sscreen,
+ unsigned char ir_sha1_cache_key[20],
struct si_shader *shader);
-bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
+void si_shader_cache_insert_shader(struct si_screen *sscreen,
+ unsigned char ir_sha1_cache_key[20],
struct si_shader *shader,
bool insert_into_disk_cache);
bool si_update_shaders(struct si_context *sctx);
struct util_queue_fence *ready_fence,
struct si_compiler_ctx_state *compiler_ctx_state,
void *job, util_queue_execute_func execute);
-void si_get_active_slot_masks(const struct tgsi_shader_info *info,
+void si_get_active_slot_masks(const struct si_shader_info *info,
uint32_t *const_and_shader_buffers,
uint64_t *samplers_and_images);
int si_shader_select_with_key(struct si_screen *sscreen,
struct si_shader_selector *vs,
struct si_shader_key *key,
struct si_vs_prolog_bits *prolog_key);
+unsigned si_get_input_prim(const struct si_shader_selector *gs);
+bool si_update_ngg(struct si_context *sctx);
/* si_state_draw.c */
void si_emit_surface_sync(struct si_context *sctx, struct radeon_cmdbuf *cs,
static inline unsigned si_get_sampler_slot(unsigned slot)
{
- /* samplers are in slots [8..39], ascending */
- return SI_NUM_IMAGES / 2 + slot;
+ /* 32 samplers are in sampler slots [16..47], 16 dw per slot, ascending */
+ /* those are equivalent to image slots [32..95], 8 dw per slot, ascending */
+ return SI_NUM_IMAGE_SLOTS / 2 + slot;
}
static inline unsigned si_get_image_slot(unsigned slot)
{
- /* images are in slots [15..0] (sampler slots [7..0]), descending */
- return SI_NUM_IMAGES - 1 - slot;
+ /* image slots are in [31..0] (sampler slots [15..0]), descending */
+ /* images are in slots [31..16], while FMASKs are in slots [15..0] */
+ return SI_NUM_IMAGE_SLOTS - 1 - slot;
}
#endif