#define SI_STATE_H
#include "radeonsi_pm4.h"
-
-/* This encapsulates a state or an operation which can emitted into the GPU
- * command stream. */
-struct si_atom {
- void (*emit)(struct r600_context *ctx, struct si_atom *state);
- unsigned num_dw;
- bool dirty;
-};
+#include "../radeon/r600_pipe_common.h"
struct si_state_blend {
struct si_pm4_state pm4;
bool flatshade;
bool two_side;
bool multisample_enable;
+ bool line_stipple_enable;
unsigned sprite_coord_enable;
unsigned pa_sc_line_stipple;
unsigned pa_su_sc_mode_cntl;
union si_state {
struct {
- struct si_pm4_state *sync;
struct si_pm4_state *init;
struct si_state_blend *blend;
struct si_pm4_state *blend_color;
struct si_pm4_state *fb_blend;
struct si_pm4_state *dsa_stencil_ref;
struct si_pm4_state *vs;
- struct si_pm4_state *vs_sampler_views;
struct si_pm4_state *vs_sampler;
- struct si_pm4_state *vs_const;
struct si_pm4_state *ps;
- struct si_pm4_state *ps_sampler_views;
struct si_pm4_state *ps_sampler;
- struct si_pm4_state *ps_const;
struct si_pm4_state *spi;
struct si_pm4_state *vertex_buffers;
- struct si_pm4_state *texture_barrier;
struct si_pm4_state *draw_info;
struct si_pm4_state *draw;
} named;
#define NUM_TEX_UNITS 16
+/* User sampler views: 0..15
+ * FMASK sampler views: 16..31 (no sampler states)
+ */
+#define FMASK_TEX_OFFSET NUM_TEX_UNITS
+#define NUM_SAMPLER_VIEWS (FMASK_TEX_OFFSET+NUM_TEX_UNITS)
+#define NUM_SAMPLER_STATES NUM_TEX_UNITS
+
+#define NUM_CONST_BUFFERS 2
+
/* This represents resource descriptors in memory, such as buffer resources,
* image resources, and sampler states.
*/
struct si_descriptors {
- struct si_atom atom;
+ struct r600_atom atom;
/* The size of one resource descriptor. */
unsigned element_dw_size;
unsigned num_elements;
/* The buffer where resource descriptors are stored. */
- struct si_resource *buffer;
+ struct r600_resource *buffer;
/* The i-th bit is set if that element is dirty (changed but not emitted). */
unsigned dirty_mask;
struct si_sampler_views {
struct si_descriptors desc;
- struct pipe_sampler_view *views[NUM_TEX_UNITS];
- const uint32_t *desc_data[NUM_TEX_UNITS];
+ struct pipe_sampler_view *views[NUM_SAMPLER_VIEWS];
+ uint32_t *desc_data[NUM_SAMPLER_VIEWS];
+};
+
+struct si_buffer_resources {
+ struct si_descriptors desc;
+ unsigned num_buffers;
+ enum radeon_bo_usage shader_usage; /* READ, WRITE, or READWRITE */
+ struct pipe_resource **buffers; /* this has num_buffers elements */
+ uint32_t *desc_storage; /* this has num_buffers*4 elements */
+ uint32_t **desc_data; /* an array of pointers pointing to desc_storage */
};
#define si_pm4_block_idx(member) \
void si_init_state_functions(struct r600_context *rctx);
void si_init_config(struct r600_context *rctx);
-/* si_state_streamout.c */
-struct pipe_stream_output_target *
-si_create_so_target(struct pipe_context *ctx,
- struct pipe_resource *buffer,
- unsigned buffer_offset,
- unsigned buffer_size);
-void si_so_target_destroy(struct pipe_context *ctx,
- struct pipe_stream_output_target *target);
-void si_set_so_targets(struct pipe_context *ctx,
- unsigned num_targets,
- struct pipe_stream_output_target **targets,
- unsigned append_bitmask);
-
/* si_state_draw.c */
+extern const struct r600_atom si_atom_cache_flush;
+void si_emit_cache_flush(struct r600_common_context *rctx, struct r600_atom *atom);
void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
/* si_commands.c */