#define SI_NUM_IMAGES 16
#define SI_NUM_SHADER_BUFFERS 16
-#define SI_TESS_OFFCHIP_BLOCK_SIZE (8192 * 4)
-
struct si_screen;
struct si_shader;
bool poly_smooth;
bool uses_poly_offset;
bool clamp_fragment_color;
+ bool clamp_vertex_color;
bool rasterizer_discard;
bool scissor_enable;
+ bool clip_halfz;
};
struct si_dsa_stencil_ref_part {
struct si_vertex_element
{
unsigned count;
+ unsigned first_vb_use_mask;
+ /* Vertex buffer descriptor list size aligned for optimal prefetch. */
+ unsigned desc_list_byte_size;
+
+ uint8_t fix_fetch[SI_MAX_ATTRIBS];
uint32_t rsrc_word3[SI_MAX_ATTRIBS];
uint32_t format_size[SI_MAX_ATTRIBS];
struct pipe_vertex_element elements[SI_MAX_ATTRIBS];
struct si_pm4_state *array[0];
};
+#define SI_NUM_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *))
+
union si_state_atoms {
struct {
/* The order matters. */
- struct r600_atom *cache_flush;
+ struct r600_atom *prefetch_L2;
struct r600_atom *render_cond;
struct r600_atom *streamout_begin;
struct r600_atom *streamout_enable; /* must be after streamout_begin */
struct r600_atom *viewports;
struct r600_atom *stencil_ref;
struct r600_atom *spi_map;
+ struct r600_atom *scratch_state;
} s;
struct r600_atom *array[0];
};
/* Private read-write buffer slots. */
enum {
- SI_HS_RING_TESS_FACTOR,
- SI_HS_RING_TESS_OFFCHIP,
-
SI_ES_RING_ESGS,
SI_GS_RING_ESGS,
- SI_GS_RING_GSVS0,
- SI_GS_RING_GSVS1,
- SI_GS_RING_GSVS2,
- SI_GS_RING_GSVS3,
- SI_VS_RING_GSVS,
+ SI_RING_GSVS,
SI_VS_STREAMOUT_BUF0,
SI_VS_STREAMOUT_BUF1,
* 21 - compute const buffers
* ...
*/
-#define SI_SHADER_DESCS_CONST_BUFFERS 0
-#define SI_SHADER_DESCS_SHADER_BUFFERS 1
-#define SI_SHADER_DESCS_SAMPLERS 2
-#define SI_SHADER_DESCS_IMAGES 3
-#define SI_NUM_SHADER_DESCS 4
+enum {
+ SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
+ SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
+ SI_NUM_SHADER_DESCS,
+};
#define SI_DESCS_RW_BUFFERS 0
#define SI_DESCS_FIRST_SHADER 1
struct si_descriptors {
/* The list of descriptors in malloc'd memory. */
uint32_t *list;
+ /* The list in mapped GPU memory. */
+ uint32_t *gpu_list;
/* The size of one descriptor. */
unsigned element_dw_size;
/* The maximum number of descriptors. */
unsigned ce_offset;
/* elements of the list that are changed and need to be uploaded */
- unsigned dirty_mask;
+ uint64_t dirty_mask;
+ /* Whether CE is used to upload this descriptor array. */
+ bool uses_ce;
/* Whether the CE ram is dirty and needs to be reinitialized entirely
* before we can do partial updates. */
bool ce_ram_dirty;
/* The shader userdata offset within a shader where the 64-bit pointer to the descriptor
* array will be stored. */
unsigned shader_userdata_offset;
- /* Whether the pointer should be re-emitted. */
- bool pointer_dirty;
};
struct si_sampler_views {
struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
- void *sampler_states[SI_NUM_SAMPLERS];
+ struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
/* The i-th bit is set if that element is enabled (non-NULL resource). */
unsigned enabled_mask;
struct si_buffer_resources {
enum radeon_bo_usage shader_usage; /* READ, WRITE, or READWRITE */
+ enum radeon_bo_usage shader_usage_constbuf;
enum radeon_bo_priority priority;
+ enum radeon_bo_priority priority_constbuf;
struct pipe_resource **buffers; /* this has num_buffers elements */
/* The i-th bit is set if that element is enabled (non-NULL resource). */
#define si_pm4_bind_state(sctx, member, value) \
do { \
(sctx)->queued.named.member = (value); \
+ (sctx)->dirty_states |= 1 << si_pm4_block_idx(member); \
} while(0)
#define si_pm4_delete_state(sctx, member, value) \
} while(0)
/* si_descriptors.c */
+void si_ce_reinitialize_all_descriptors(struct si_context *sctx);
void si_ce_enable_loads(struct radeon_winsys_cs *ib);
-void si_set_mutable_tex_desc_fields(struct r600_texture *tex,
- const struct radeon_surf_level *base_level_info,
- unsigned base_level, unsigned block_width,
- bool is_stencil, uint32_t *state);
+void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
+ struct r600_texture *tex,
+ const struct legacy_surf_level *base_level_info,
+ unsigned base_level, unsigned first_level,
+ unsigned block_width, bool is_stencil,
+ uint32_t *state);
+void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader,
+ uint slot, struct pipe_constant_buffer *cbuf);
+void si_get_shader_buffers(struct si_context *sctx,
+ enum pipe_shader_type shader,
+ uint start_slot, uint count,
+ struct pipe_shader_buffer *sbuf);
void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
struct pipe_resource *buffer,
unsigned stride, unsigned num_records,
bool add_tid, bool swizzle,
unsigned element_size, unsigned index_stride, uint64_t offset);
void si_init_all_descriptors(struct si_context *sctx);
+bool si_upload_vertex_buffer_descriptors(struct si_context *sctx);
bool si_upload_graphics_shader_descriptors(struct si_context *sctx);
bool si_upload_compute_shader_descriptors(struct si_context *sctx);
void si_release_all_descriptors(struct si_context *sctx);
struct r600_atom *atom);
void si_emit_compute_shader_userdata(struct si_context *sctx);
void si_set_rw_buffer(struct si_context *sctx,
- uint slot, struct pipe_constant_buffer *input);
-
+ uint slot, const struct pipe_constant_buffer *input);
/* si_state.c */
struct si_shader_selector;
void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
struct r600_atom **list_elem,
void (*emit_func)(struct si_context *ctx, struct r600_atom *state));
-boolean si_is_format_supported(struct pipe_screen *screen,
- enum pipe_format format,
- enum pipe_texture_target target,
- unsigned sample_count,
- unsigned usage);
void si_init_state_functions(struct si_context *sctx);
void si_init_screen_state_functions(struct si_screen *sscreen);
void
si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
enum pipe_format format,
- unsigned first_element, unsigned last_element,
+ unsigned offset, unsigned size,
uint32_t *state);
void
si_make_texture_descriptor(struct si_screen *screen,
const struct pipe_sampler_view *state,
unsigned width0, unsigned height0,
unsigned force_level);
-void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state);
/* si_state_shader.c */
bool si_update_shaders(struct si_context *sctx);
void si_init_shader_functions(struct si_context *sctx);
bool si_init_shader_cache(struct si_screen *sscreen);
void si_destroy_shader_cache(struct si_screen *sscreen);
+void si_init_shader_selector_async(void *job, int thread_index);
/* si_state_draw.c */
-void si_emit_cache_flush(struct si_context *sctx, struct r600_atom *atom);
+void si_init_ia_multi_vgt_param_table(struct si_context *sctx);
+void si_emit_cache_flush(struct si_context *sctx);
void si_ce_pre_draw_synchronization(struct si_context *sctx);
void si_ce_post_draw_synchronization(struct si_context *sctx);
void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
{
if (stencil)
- return rtex->surface.stencil_tiling_index[level];
+ return rtex->surface.u.legacy.stencil_tiling_index[level];
else
- return rtex->surface.tiling_index[level];
+ return rtex->surface.u.legacy.tiling_index[level];
+}
+
+static inline unsigned si_get_constbuf_slot(unsigned slot)
+{
+ /* Constant buffers are in slots [16..31], ascending */
+ return SI_NUM_SHADER_BUFFERS + slot;
+}
+
+static inline unsigned si_get_shaderbuf_slot(unsigned slot)
+{
+ /* shader buffers are in slots [15..0], descending */
+ return SI_NUM_SHADER_BUFFERS - 1 - slot;
+}
+
+static inline unsigned si_get_sampler_slot(unsigned slot)
+{
+ /* samplers are in slots [8..39], ascending */
+ return SI_NUM_IMAGES / 2 + slot;
+}
+
+static inline unsigned si_get_image_slot(unsigned slot)
+{
+ /* images are in slots [15..0] (sampler slots [7..0]), descending */
+ return SI_NUM_IMAGES - 1 - slot;
}
#endif
projects / mesa.git / blobdiff