radeonsi: merge sampler and image descriptor lists into one

[mesa.git] / src / gallium / drivers / radeonsi / si_state.h

diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index e06b4d1d7d9b4588910fd1beee72540a2fb7cafa..c4ef90372fb9697be22b5a40ed243cb90137084e 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -74,6 +74,7 @@ struct si_state_rasterizer {
        bool                    poly_smooth;
        bool                    uses_poly_offset;
        bool                    clamp_fragment_color;
+       bool                    clamp_vertex_color;
        bool                    rasterizer_discard;
        bool                    scissor_enable;
        bool                    clip_halfz;
@@ -163,9 +164,6 @@ struct si_shader_data {
 
 /* Private read-write buffer slots. */
 enum {
-       SI_HS_RING_TESS_FACTOR,
-       SI_HS_RING_TESS_OFFCHIP,
-
        SI_ES_RING_ESGS,
        SI_GS_RING_ESGS,
 
@@ -196,11 +194,11 @@ enum {
  *  21 - compute const buffers
  *   ...
  */
-#define SI_SHADER_DESCS_CONST_BUFFERS  0
-#define SI_SHADER_DESCS_SHADER_BUFFERS 1
-#define SI_SHADER_DESCS_SAMPLERS       2
-#define SI_SHADER_DESCS_IMAGES         3
-#define SI_NUM_SHADER_DESCS            4
+enum {
+       SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS,
+       SI_SHADER_DESCS_SAMPLERS_AND_IMAGES,
+       SI_NUM_SHADER_DESCS,
+};
 
 #define SI_DESCS_RW_BUFFERS            0
 #define SI_DESCS_FIRST_SHADER          1
@@ -230,8 +228,10 @@ struct si_descriptors {
        unsigned ce_offset;
 
        /* elements of the list that are changed and need to be uploaded */
-       unsigned dirty_mask;
+       uint64_t dirty_mask;
 
+       /* Whether CE is used to upload this descriptor array. */
+       bool uses_ce;
        /* Whether the CE ram is dirty and needs to be reinitialized entirely
         * before we can do partial updates. */
        bool ce_ram_dirty;
@@ -251,7 +251,9 @@ struct si_sampler_views {
 
 struct si_buffer_resources {
        enum radeon_bo_usage            shader_usage; /* READ, WRITE, or READWRITE */
+       enum radeon_bo_usage            shader_usage_constbuf;
        enum radeon_bo_priority         priority;
+       enum radeon_bo_priority         priority_constbuf;
        struct pipe_resource            **buffers; /* this has num_buffers elements */
 
        /* The i-th bit is set if that element is enabled (non-NULL resource). */
@@ -372,4 +374,28 @@ si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
                return rtex->surface.u.legacy.tiling_index[level];
 }
 
+static inline unsigned si_get_constbuf_slot(unsigned slot)
+{
+       /* Constant buffers are in slots [16..31], ascending */
+       return SI_NUM_SHADER_BUFFERS + slot;
+}
+
+static inline unsigned si_get_shaderbuf_slot(unsigned slot)
+{
+       /* shader buffers are in slots [15..0], descending */
+       return SI_NUM_SHADER_BUFFERS - 1 - slot;
+}
+
+static inline unsigned si_get_sampler_slot(unsigned slot)
+{
+       /* samplers are in slots [8..39], ascending */
+       return SI_NUM_IMAGES / 2 + slot;
+}
+
+static inline unsigned si_get_image_slot(unsigned slot)
+{
+       /* images are in slots [15..0] (sampler slots [7..0]), descending */
+       return SI_NUM_IMAGES - 1 - slot;
+}
+
 #endif