radeonsi: set DB_EQAA the same as Vulkan

[mesa.git] / src / gallium / drivers / radeonsi / si_state_binning.c

diff --git a/src/gallium/drivers/radeonsi/si_state_binning.c b/src/gallium/drivers/radeonsi/si_state_binning.c
index 0f50ea755cbff4eae122d1a4f4365b12d0a34a15..80b1137fd0c90b9193cc3bee9f9826e510975d5a 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_binning.c
+++ b/src/gallium/drivers/radeonsi/si_state_binning.c
@@ -1,5 +1,6 @@
 /*
  * Copyright 2017 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -23,10 +24,8 @@
 
 /* This file handles register programming of primitive binning. */
 
-#include "si_pipe.h"
-#include "sid.h"
+#include "si_build_pm4.h"
 #include "gfx9d.h"
-#include "radeon/r600_cs.h"
 
 struct uvec2 {
        unsigned x, y;
@@ -82,7 +81,7 @@ static struct uvec2 si_get_color_bin_size(struct si_context *sctx,
 
        /* Multiply the sum by some function of the number of samples. */
        if (nr_samples >= 2) {
-               if (sctx->ps_iter_samples >= 2)
+               if (si_get_ps_iter_samples(sctx) >= 2)
                        sum *= nr_samples;
                else
                        sum *= 2;
@@ -326,7 +325,7 @@ static struct uvec2 si_get_depth_bin_size(struct si_context *sctx)
 
 static void si_emit_dpbb_disable(struct si_context *sctx)
 {
-       struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
+       struct radeon_winsys_cs *cs = sctx->gfx_cs;
 
        radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
                               S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
@@ -335,14 +334,14 @@ static void si_emit_dpbb_disable(struct si_context *sctx)
                               S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF));
 }
 
-void si_emit_dpbb_state(struct si_context *sctx, struct r600_atom *state)
+void si_emit_dpbb_state(struct si_context *sctx)
 {
        struct si_screen *sscreen = sctx->screen;
        struct si_state_blend *blend = sctx->queued.named.blend;
        struct si_state_dsa *dsa = sctx->queued.named.dsa;
        unsigned db_shader_control = sctx->ps_db_shader_control;
 
-       assert(sctx->b.chip_class >= GFX9);
+       assert(sctx->chip_class >= GFX9);
 
        if (!sscreen->dpbb_allowed || !blend || !dsa) {
                si_emit_dpbb_disable(sctx);
@@ -412,7 +411,7 @@ void si_emit_dpbb_state(struct si_context *sctx, struct r600_atom *state)
        unsigned persistent_states_per_bin; /* allowed range: [0, 31] */
        unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
 
-       switch (sctx->b.family) {
+       switch (sctx->family) {
        case CHIP_VEGA10:
        case CHIP_VEGA12:
        case CHIP_RAVEN:
@@ -432,7 +431,7 @@ void si_emit_dpbb_state(struct si_context *sctx, struct r600_atom *state)
        if (bin_size.y >= 32)
                bin_size_extend.y = util_logbase2(bin_size.y) - 5;
 
-       struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
+       struct radeon_winsys_cs *cs = sctx->gfx_cs;
        radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
                               S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
                               S_028C44_BIN_SIZE_X(bin_size.x == 16) |