nir: Add lower_rotate flag and set to true in all drivers

[mesa.git] / src / gallium / drivers / radeonsi / si_state_binning.c

diff --git a/src/gallium/drivers/radeonsi/si_state_binning.c b/src/gallium/drivers/radeonsi/si_state_binning.c
index b68c637e1e2209f77782f436dd063f3e3d8f211d..a6b1830b661b160679f26dbf7d2a92001e2dd9a9 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_binning.c
+++ b/src/gallium/drivers/radeonsi/si_state_binning.c
@@ -25,7 +25,7 @@
 /* This file handles register programming of primitive binning. */
 
 #include "si_build_pm4.h"
-#include "gfx9d.h"
+#include "sid.h"
 
 struct uvec2 {
        unsigned x, y;
@@ -310,6 +310,8 @@ static struct uvec2 si_get_depth_bin_size(struct si_context *sctx)
 
 static void si_emit_dpbb_disable(struct si_context *sctx)
 {
+       unsigned initial_cdw = sctx->gfx_cs->current.cdw;
+
        radeon_opt_set_context_reg(sctx, R_028C44_PA_SC_BINNER_CNTL_0,
                SI_TRACKED_PA_SC_BINNER_CNTL_0,
                S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
@@ -318,6 +320,8 @@ static void si_emit_dpbb_disable(struct si_context *sctx)
                                   SI_TRACKED_DB_DFSM_CONTROL,
                                   S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF) |
                                   S_028060_POPS_DRAIN_PS_ON_OVERLAP(1));
+       if (initial_cdw != sctx->gfx_cs->current.cdw)
+               sctx->context_roll = true;
 }
 
 void si_emit_dpbb_state(struct si_context *sctx)
@@ -398,18 +402,10 @@ void si_emit_dpbb_state(struct si_context *sctx)
        unsigned persistent_states_per_bin; /* allowed range: [0, 31] */
        unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
 
-       switch (sctx->family) {
-       case CHIP_VEGA10:
-       case CHIP_VEGA12:
-       case CHIP_RAVEN:
-               /* Tuned for Raven. Vega might need different values. */
-               context_states_per_bin = 5;
-               persistent_states_per_bin = 31;
-               fpovs_per_batch = 63;
-               break;
-       default:
-               assert(0);
-       }
+       /* Tuned for Raven. Vega might need different values. */
+       context_states_per_bin = 5;
+       persistent_states_per_bin = 31;
+       fpovs_per_batch = 63;
 
        /* Emit registers. */
        struct uvec2 bin_size_extend = {};
@@ -418,6 +414,7 @@ void si_emit_dpbb_state(struct si_context *sctx)
        if (bin_size.y >= 32)
                bin_size_extend.y = util_logbase2(bin_size.y) - 5;
 
+       unsigned initial_cdw = sctx->gfx_cs->current.cdw;
        radeon_opt_set_context_reg(
                sctx, R_028C44_PA_SC_BINNER_CNTL_0,
                SI_TRACKED_PA_SC_BINNER_CNTL_0,
@@ -435,4 +432,6 @@ void si_emit_dpbb_state(struct si_context *sctx)
                                   SI_TRACKED_DB_DFSM_CONTROL,
                                   S_028060_PUNCHOUT_MODE(punchout_mode) |
                                   S_028060_POPS_DRAIN_PS_ON_OVERLAP(1));
+       if (initial_cdw != sctx->gfx_cs->current.cdw)
+               sctx->context_roll = true;
 }