return;
va = r600_resource_va(ctx->screen, (void *)shader->bo);
- si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
+ si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
S_00B32C_USER_SGPR(num_user_sgprs));
- si_pm4_bind_state(sctx, es, shader->pm4);
sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
}
si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize);
va = r600_resource_va(ctx->screen, (void *)shader->bo);
- si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
+ si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
S_00B22C_USER_SGPR(num_user_sgprs));
- si_pm4_bind_state(sctx, gs, shader->pm4);
sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
}
return;
va = r600_resource_va(ctx->screen, (void *)shader->bo);
- si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
+ si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
S_00B12C_SO_EN(!!shader->selector->so.num_outputs));
- si_pm4_bind_state(sctx, vs, shader->pm4);
sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
}
return;
db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
- S_02880C_ALPHA_TO_MASK_DISABLE(sctx->fb_cb0_is_integer);
+ S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer);
for (i = 0; i < shader->shader.ninput; i++) {
switch (shader->shader.input[i].name) {
si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
va = r600_resource_va(ctx->screen, (void *)shader->bo);
- si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
+ si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
- shader->cb0_is_integer = sctx->fb_cb0_is_integer;
+ shader->cb0_is_integer = sctx->framebuffer.cb0_is_integer;
shader->sprite_coord_enable = sctx->sprite_coord_enable;
- si_pm4_bind_state(sctx, ps, shader->pm4);
sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
}
[PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
[PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
[PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
- [PIPE_PRIM_LINES_ADJACENCY] = ~0,
- [PIPE_PRIM_LINE_STRIP_ADJACENCY] = ~0,
- [PIPE_PRIM_TRIANGLES_ADJACENCY] = ~0,
- [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = ~0
+ [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
+ [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
+ [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
+ [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ
};
unsigned result = prim_conv[pprim];
if (result == ~0) {
const struct pipe_index_buffer *ib)
{
struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
- struct si_shader *vs = &sctx->vs_shader->current->shader;
+ struct si_shader *vs = si_get_vs_state(sctx);
unsigned prim = si_conv_pipe_prim(info->mode);
unsigned gs_out_prim =
si_conv_prim_to_gs_out(sctx->gs_shader ?
static void si_update_spi_map(struct si_context *sctx)
{
struct si_shader *ps = &sctx->ps_shader->current->shader;
- struct si_shader *vs = &sctx->vs_shader->current->shader;
+ struct si_shader *vs = si_get_vs_state(sctx);
struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
unsigned i, j, tmp;
sctx->esgs_ring.buffer =
pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
- PIPE_USAGE_STATIC, size);
+ PIPE_USAGE_DEFAULT, size);
sctx->esgs_ring.buffer_size = size;
size = 64 * 1024 * 1024;
sctx->gsvs_ring.buffer =
pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
- PIPE_USAGE_STATIC, size);
+ PIPE_USAGE_DEFAULT, size);
sctx->gsvs_ring.buffer_size = size;
if (sctx->b.chip_class >= CIK) {
sctx->gsvs_ring.buffer_size / 256);
}
- si_set_ring_buffer(&sctx->b.b, SI_SHADER_EXPORT, 0, &sctx->esgs_ring,
- 0, sctx->esgs_ring.buffer_size, true, true, 4, 64);
- si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, 0, &sctx->esgs_ring,
- 0, sctx->esgs_ring.buffer_size, false, false, 0, 0);
- si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, 0, &sctx->gsvs_ring,
- 0, sctx->gsvs_ring.buffer_size, false, false, 0, 0);
+ si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
+ &sctx->esgs_ring, 0, sctx->esgs_ring.buffer_size,
+ true, true, 4, 64);
+ si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
+ &sctx->esgs_ring, 0, sctx->esgs_ring.buffer_size,
+ false, false, 0, 0);
+ si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
+ &sctx->gsvs_ring, 0, sctx->gsvs_ring.buffer_size,
+ false, false, 0, 0);
}
static void si_update_derived_state(struct si_context *sctx)
{
struct pipe_context * ctx = (struct pipe_context*)sctx;
- unsigned vs_dirty = 0, ps_dirty = 0;
if (!sctx->blitter->running) {
/* Flush depth textures which need to be flushed. */
}
if (sctx->gs_shader) {
- unsigned es_dirty = 0, gs_dirty = 0;
-
- si_shader_select(ctx, sctx->gs_shader, &gs_dirty);
+ si_shader_select(ctx, sctx->gs_shader);
if (!sctx->gs_shader->current->pm4) {
si_pipe_shader_gs(ctx, sctx->gs_shader->current);
si_pipe_shader_vs(ctx,
sctx->gs_shader->current->gs_copy_shader);
- gs_dirty = 0;
}
- if (gs_dirty) {
- si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
- si_pm4_bind_state(sctx, vs,
- sctx->gs_shader->current->gs_copy_shader->pm4);
- }
+ si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
+ si_pm4_bind_state(sctx, vs, sctx->gs_shader->current->gs_copy_shader->pm4);
+
+ sctx->b.streamout.stride_in_dw = sctx->gs_shader->so.stride;
- si_shader_select(ctx, sctx->vs_shader, &es_dirty);
+ si_shader_select(ctx, sctx->vs_shader);
- if (!sctx->vs_shader->current->pm4) {
+ if (!sctx->vs_shader->current->pm4)
si_pipe_shader_es(ctx, sctx->vs_shader->current);
- es_dirty = 0;
- }
- if (es_dirty) {
- si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4);
- }
+ si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4);
if (!sctx->gs_rings)
si_init_gs_rings(sctx);
sctx->b.flags |= R600_CONTEXT_VGT_FLUSH;
si_pm4_bind_state(sctx, gs_rings, sctx->gs_rings);
- si_set_ring_buffer(ctx, PIPE_SHADER_GEOMETRY, 1, &sctx->gsvs_ring,
+ si_set_ring_buffer(ctx, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
+ &sctx->gsvs_ring,
sctx->gs_shader->current->shader.gs_max_out_vertices *
sctx->gs_shader->current->shader.noutput * 16,
64, true, true, 4, 16);
}
si_pm4_bind_state(sctx, gs_onoff, sctx->gs_on);
} else {
- si_shader_select(ctx, sctx->vs_shader, &vs_dirty);
+ si_shader_select(ctx, sctx->vs_shader);
- if (!sctx->vs_shader->current->pm4) {
+ if (!sctx->vs_shader->current->pm4)
si_pipe_shader_vs(ctx, sctx->vs_shader->current);
- vs_dirty = 0;
- }
- if (vs_dirty) {
- si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
- }
+ si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
+
+ sctx->b.streamout.stride_in_dw = sctx->vs_shader->so.stride;
if (!sctx->gs_off) {
sctx->gs_off = si_pm4_alloc_state(sctx);
si_pm4_bind_state(sctx, es, NULL);
}
- si_shader_select(ctx, sctx->ps_shader, &ps_dirty);
+ si_shader_select(ctx, sctx->ps_shader);
- if (!sctx->ps_shader->current->pm4) {
- si_pipe_shader_ps(ctx, sctx->ps_shader->current);
- ps_dirty = 0;
- }
- if (sctx->ps_shader->current->cb0_is_integer != sctx->fb_cb0_is_integer) {
+ if (!sctx->ps_shader->current->pm4 ||
+ sctx->ps_shader->current->cb0_is_integer != sctx->framebuffer.cb0_is_integer)
si_pipe_shader_ps(ctx, sctx->ps_shader->current);
- ps_dirty = 0;
- }
- if (ps_dirty) {
- si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
- }
+ si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs)) {
/* XXX: Emitting the PS state even when only the VS changed
si_pm4_sh_data_add(pm4, sctx->vertex_elements->rsrc_word3[i]);
if (!bound[ve->vertex_buffer_index]) {
- si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
+ si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ,
+ RADEON_PRIO_SHADER_BUFFER_RO);
bound[ve->vertex_buffer_index] = true;
}
}
if (sctx->b.chip_class >= CIK) {
si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
S_028004_PERFECT_ZPASS_COUNTS(1) |
- S_028004_SAMPLE_RATE(sctx->fb_log_samples) |
+ S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
S_028004_ZPASS_ENABLE(1) |
S_028004_SLICE_EVEN_ENABLE(1) |
S_028004_SLICE_ODD_ENABLE(1));
} else {
si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
S_028004_PERFECT_ZPASS_COUNTS(1) |
- S_028004_SAMPLE_RATE(sctx->fb_log_samples));
+ S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
}
}
si_pm4_cmd_add(pm4, va >> 32UL); /* src address hi */
si_pm4_cmd_add(pm4, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
si_pm4_cmd_add(pm4, 0); /* unused */
- si_pm4_add_bo(pm4, t->buf_filled_size, RADEON_USAGE_READ);
+ si_pm4_add_bo(pm4, t->buf_filled_size, RADEON_USAGE_READ,
+ RADEON_PRIO_MIN);
si_pm4_cmd_end(pm4, true);
}
va = r600_resource_va(&sctx->screen->b.b, ib->buffer);
va += ib->offset;
- si_pm4_add_bo(pm4, (struct r600_resource *)ib->buffer, RADEON_USAGE_READ);
+ si_pm4_add_bo(pm4, (struct r600_resource *)ib->buffer, RADEON_USAGE_READ,
+ RADEON_PRIO_MIN);
si_cmd_draw_index_2(pm4, max_size, va, info->count,
V_0287F0_DI_SRC_SEL_DMA,
sctx->b.predicate_drawing);
#endif
/* Set the depth buffer as dirty. */
- if (sctx->framebuffer.zsbuf) {
- struct pipe_surface *surf = sctx->framebuffer.zsbuf;
+ if (sctx->framebuffer.state.zsbuf) {
+ struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
struct r600_texture *rtex = (struct r600_texture *)surf->texture;
rtex->dirty_level_mask |= 1 << surf->u.tex.level;
}
- if (sctx->fb_compressed_cb_mask) {
+ if (sctx->framebuffer.compressed_cb_mask) {
struct pipe_surface *surf;
struct r600_texture *rtex;
- unsigned mask = sctx->fb_compressed_cb_mask;
+ unsigned mask = sctx->framebuffer.compressed_cb_mask;
do {
unsigned i = u_bit_scan(&mask);
- surf = sctx->framebuffer.cbufs[i];
+ surf = sctx->framebuffer.state.cbufs[i];
rtex = (struct r600_texture*)surf->texture;
rtex->dirty_level_mask |= 1 << surf->u.tex.level;
projects / mesa.git / blobdiff