if (sctx->tcs_shader.cso) {
num_tcs_outputs = util_last_bit64(tcs->outputs_written);
- num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
+ num_tcs_output_cp = tcs->info.base.tess.tcs_vertices_out;
num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
} else {
/* No TCS. Route varyings from LS to TES. */
static unsigned si_conv_prim_to_gs_out(unsigned mode)
{
static const int prim_conv[] = {
- [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
- [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
- [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
- [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
- [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
- [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
- [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
- [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
- [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
- [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
- [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
- [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
- [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
- [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
- [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
- [SI_PRIM_RECTANGLE_LIST] = V_028A6C_VGT_OUT_RECT_V0,
+ [PIPE_PRIM_POINTS] = V_028A6C_POINTLIST,
+ [PIPE_PRIM_LINES] = V_028A6C_LINESTRIP,
+ [PIPE_PRIM_LINE_LOOP] = V_028A6C_LINESTRIP,
+ [PIPE_PRIM_LINE_STRIP] = V_028A6C_LINESTRIP,
+ [PIPE_PRIM_TRIANGLES] = V_028A6C_TRISTRIP,
+ [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_TRISTRIP,
+ [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_TRISTRIP,
+ [PIPE_PRIM_QUADS] = V_028A6C_TRISTRIP,
+ [PIPE_PRIM_QUAD_STRIP] = V_028A6C_TRISTRIP,
+ [PIPE_PRIM_POLYGON] = V_028A6C_TRISTRIP,
+ [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_LINESTRIP,
+ [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_LINESTRIP,
+ [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_TRISTRIP,
+ [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_TRISTRIP,
+ [PIPE_PRIM_PATCHES] = V_028A6C_POINTLIST,
+ [SI_PRIM_RECTANGLE_LIST] = V_028A6C_RECTLIST,
};
assert(mode < ARRAY_SIZE(prim_conv));
/* draw packet */
if (index_size) {
- if (index_size != sctx->last_index_size) {
+ /* Register shadowing doesn't shadow INDEX_TYPE. */
+ if (index_size != sctx->last_index_size || sctx->shadowed_regs) {
unsigned index_type;
/* index type */
} else {
int base_vertex;
- if (sctx->last_instance_count == SI_INSTANCE_COUNT_UNKNOWN ||
+ /* Register shadowing requires that we always emit PKT3_NUM_INSTANCES. */
+ if (sctx->shadowed_regs ||
+ sctx->last_instance_count == SI_INSTANCE_COUNT_UNKNOWN ||
sctx->last_instance_count != instance_count) {
radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
radeon_emit(cs, instance_count);
/* Samplers. */
struct si_shader_selector *vs = sctx->vs_shader.cso;
- if (vs->info.samplers_declared) {
- unsigned num_samplers = util_last_bit(vs->info.samplers_declared);
+ if (vs->info.base.textures_used) {
+ unsigned num_samplers = util_last_bit(vs->info.base.textures_used);
for (unsigned i = 0; i < num_samplers; i++) {
struct pipe_sampler_view *view = sctx->samplers[PIPE_SHADER_VERTEX].views[i];
}
/* Images. */
- if (vs->info.images_declared) {
- unsigned num_images = util_last_bit(vs->info.images_declared);
-
+ unsigned num_images = vs->info.base.num_images;
+ if (num_images) {
for (unsigned i = 0; i < num_images; i++) {
struct pipe_resource *res = sctx->images[PIPE_SHADER_VERTEX].views[i].resource;
if (!res)
*/
struct si_shader_selector *tcs = sctx->tcs_shader.cso;
bool ls_vgpr_fix =
- tcs && info->vertices_per_patch > tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
+ tcs && info->vertices_per_patch > tcs->info.base.tess.tcs_vertices_out;
if (ls_vgpr_fix != sctx->ls_vgpr_fix) {
sctx->ls_vgpr_fix = ls_vgpr_fix;
(!sctx->vs_shader.cso->info.uses_bindless_samplers || pd_msg("uses bindless samplers")) &&
(!sctx->vs_shader.cso->info.writes_memory || pd_msg("writes memory")) &&
(!sctx->vs_shader.cso->info.writes_viewport_index || pd_msg("writes viewport index")) &&
- !sctx->vs_shader.cso->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
+ !sctx->vs_shader.cso->info.base.vs.window_space_position &&
!sctx->vs_shader.cso->so.num_outputs &&
#else
(sctx->vs_shader.cso->prim_discard_cs_allowed ||
/* Update NGG culling settings. */
if (sctx->ngg && !dispatch_prim_discard_cs && rast_prim == PIPE_PRIM_TRIANGLES &&
- (sctx->screen->always_use_ngg_culling ||
+ !sctx->gs_shader.cso && /* GS doesn't support NGG culling. */
+ (sctx->screen->always_use_ngg_culling_all ||
+ (sctx->tes_shader.cso && sctx->screen->always_use_ngg_culling_tess) ||
/* At least 1024 non-indexed vertices (8 subgroups) are needed
* per draw call (no TES/GS) to enable NGG culling.
*/
(!index_size && direct_count >= 1024 &&
(prim == PIPE_PRIM_TRIANGLES || prim == PIPE_PRIM_TRIANGLE_STRIP) &&
- !sctx->tes_shader.cso && !sctx->gs_shader.cso)) &&
+ !sctx->tes_shader.cso)) &&
si_get_vs(sctx)->cso->ngg_culling_allowed) {
unsigned ngg_culling = 0;
si_need_gfx_cs_space(sctx);
+ /* If we're using a secure context, determine if cs must be secure or not */
+ if (unlikely(sctx->ws->ws_is_secure(sctx->ws))) {
+ bool secure = si_gfx_resources_check_encrypted(sctx);
+ if (secure != sctx->ws->cs_is_secure(sctx->gfx_cs)) {
+ si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
+ sctx->ws->cs_set_secure(sctx->gfx_cs, secure);
+ }
+ }
+
if (sctx->bo_list_add_all_gfx_resources)
si_gfx_resources_add_all_to_bo_list(sctx);