amd,radeonsi: rename radeon_winsys_cs -> radeon_cmdbuf

[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 5370587d747920c4bb7317bfbb0bae7f3eea7985..2291b4a00addb7631b4488fcc6b763dd976cff13 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -70,7 +70,7 @@ static bool si_emit_derived_tess_state(struct si_context *sctx,
                                       const struct pipe_draw_info *info,
                                       unsigned *num_patches)
 {
-       struct radeon_winsys_cs *cs = sctx->gfx_cs;
+       struct radeon_cmdbuf *cs = sctx->gfx_cs;
        struct si_shader *ls_current;
        struct si_shader_selector *ls;
        /* The TES pointer will only be used for sctx->last_tcs.
@@ -146,7 +146,8 @@ static bool si_emit_derived_tess_state(struct si_context *sctx,
         * resource usage. Also ensures that the number of tcs in and out
         * vertices per threadgroup are at most 256.
         */
-       *num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
+       unsigned max_verts_per_patch = MAX2(num_tcs_input_cp, num_tcs_output_cp);
+       *num_patches = 256 / max_verts_per_patch;
 
        /* Make sure that the data fits in LDS. This assumes the shaders only
         * use LDS for the inputs and outputs.
@@ -164,16 +165,31 @@ static bool si_emit_derived_tess_state(struct si_context *sctx,
                            (sctx->screen->tess_offchip_block_dw_size * 4) /
                            output_patch_size);
 
-       /* Not necessary for correctness, but improves performance. The
-        * specific value is taken from the proprietary driver.
+       /* Not necessary for correctness, but improves performance.
+        * The hardware can do more, but the radeonsi shader constant is
+        * limited to 6 bits.
         */
-       *num_patches = MIN2(*num_patches, 40);
+       *num_patches = MIN2(*num_patches, 63); /* triangles: 3 full waves except 3 lanes */
+
+       /* When distributed tessellation is unsupported, switch between SEs
+        * at a higher frequency to compensate for it.
+        */
+       if (!sctx->screen->has_distributed_tess && sctx->screen->info.max_se > 1)
+               *num_patches = MIN2(*num_patches, 16); /* recommended */
+
+       /* Make sure that vector lanes are reasonably occupied. It probably
+        * doesn't matter much because this is LS-HS, and TES is likely to
+        * occupy significantly more CUs.
+        */
+       unsigned temp_verts_per_tg = *num_patches * max_verts_per_patch;
+       if (temp_verts_per_tg > 64 && temp_verts_per_tg % 64 < 48)
+               *num_patches = (temp_verts_per_tg & ~63) / max_verts_per_patch;
 
        if (sctx->chip_class == SI) {
                /* SI bug workaround, related to power management. Limit LS-HS
                 * threadgroups to only one wave.
                 */
-               unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
+               unsigned one_wave = 64 / max_verts_per_patch;
                *num_patches = MIN2(*num_patches, one_wave);
        }
 
@@ -516,7 +532,7 @@ static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
 /* rast_prim is the primitive type after GS. */
 static bool si_emit_rasterizer_prim_state(struct si_context *sctx)
 {
-       struct radeon_winsys_cs *cs = sctx->gfx_cs;
+       struct radeon_cmdbuf *cs = sctx->gfx_cs;
        enum pipe_prim_type rast_prim = sctx->current_rast_prim;
        struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
 
@@ -553,7 +569,7 @@ static void si_emit_vs_state(struct si_context *sctx,
        }
 
        if (sctx->current_vs_state != sctx->last_vs_state) {
-               struct radeon_winsys_cs *cs = sctx->gfx_cs;
+               struct radeon_cmdbuf *cs = sctx->gfx_cs;
 
                radeon_set_sh_reg(cs,
                        sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] +
@@ -576,7 +592,7 @@ static void si_emit_draw_registers(struct si_context *sctx,
                                   const struct pipe_draw_info *info,
                                   unsigned num_patches)
 {
-       struct radeon_winsys_cs *cs = sctx->gfx_cs;
+       struct radeon_cmdbuf *cs = sctx->gfx_cs;
        unsigned prim = si_conv_pipe_prim(info->mode);
        unsigned ia_multi_vgt_param;
 
@@ -628,7 +644,7 @@ static void si_emit_draw_packets(struct si_context *sctx,
                                 unsigned index_offset)
 {
        struct pipe_draw_indirect_info *indirect = info->indirect;
-       struct radeon_winsys_cs *cs = sctx->gfx_cs;
+       struct radeon_cmdbuf *cs = sctx->gfx_cs;
        unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX];
        bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
        uint32_t index_max_size = 0;
@@ -830,7 +846,7 @@ static void si_emit_draw_packets(struct si_context *sctx,
 static void si_emit_surface_sync(struct si_context *sctx,
                                 unsigned cp_coher_cntl)
 {
-       struct radeon_winsys_cs *cs = sctx->gfx_cs;
+       struct radeon_cmdbuf *cs = sctx->gfx_cs;
 
        if (sctx->chip_class >= GFX9) {
                /* Flush caches and wait for the caches to assert idle. */
@@ -853,7 +869,7 @@ static void si_emit_surface_sync(struct si_context *sctx,
 
 void si_emit_cache_flush(struct si_context *sctx)
 {
-       struct radeon_winsys_cs *cs = sctx->gfx_cs;
+       struct radeon_cmdbuf *cs = sctx->gfx_cs;
        uint32_t flags = sctx->flags;
        uint32_t cp_coher_cntl = 0;
        uint32_t flush_cb_db = flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
@@ -1229,15 +1245,10 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
                        return;
        }
 
-       if (unlikely(!sctx->vs_shader.cso)) {
-               assert(0);
-               return;
-       }
-       if (unlikely(!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard))) {
-               assert(0);
-               return;
-       }
-       if (unlikely(!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES))) {
+       if (unlikely(!sctx->vs_shader.cso ||
+                    !rs ||
+                    (!sctx->ps_shader.cso && !rs->rasterizer_discard) ||
+                    (!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES)))) {
                assert(0);
                return;
        }
@@ -1537,7 +1548,7 @@ void si_draw_rectangle(struct blitter_context *blitter,
 
 void si_trace_emit(struct si_context *sctx)
 {
-       struct radeon_winsys_cs *cs = sctx->gfx_cs;
+       struct radeon_cmdbuf *cs = sctx->gfx_cs;
        uint64_t va = sctx->current_saved_cs->trace_buf->gpu_address;
        uint32_t trace_id = ++sctx->current_saved_cs->trace_id;