radeonsi: fix freeing descriptor buffers

[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 7ccfb58d702ca377249dcc9cc77ed9532f725a21..480e3f8a52013be76312628d5bc4aa36e6131f7a 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -548,13 +548,13 @@ static void si_init_gs_rings(struct si_context *sctx)
 
        sctx->esgs_ring.buffer =
                pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
-                                  PIPE_USAGE_STATIC, size);
+                                  PIPE_USAGE_DEFAULT, size);
        sctx->esgs_ring.buffer_size = size;
 
        size = 64 * 1024 * 1024;
        sctx->gsvs_ring.buffer =
                pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
-                                  PIPE_USAGE_STATIC, size);
+                                  PIPE_USAGE_DEFAULT, size);
        sctx->gsvs_ring.buffer_size = size;
 
        if (sctx->b.chip_class >= CIK) {
@@ -569,12 +569,15 @@ static void si_init_gs_rings(struct si_context *sctx)
                               sctx->gsvs_ring.buffer_size / 256);
        }
 
-       si_set_ring_buffer(&sctx->b.b, SI_SHADER_EXPORT, 0, &sctx->esgs_ring,
-                          0, sctx->esgs_ring.buffer_size, true, true, 4, 64);
-       si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, 0, &sctx->esgs_ring,
-                          0, sctx->esgs_ring.buffer_size, false, false, 0, 0);
-       si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, 0, &sctx->gsvs_ring,
-                          0, sctx->gsvs_ring.buffer_size, false, false, 0, 0);
+       si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
+                          &sctx->esgs_ring, 0, sctx->esgs_ring.buffer_size,
+                          true, true, 4, 64);
+       si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
+                          &sctx->esgs_ring, 0, sctx->esgs_ring.buffer_size,
+                          false, false, 0, 0);
+       si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
+                          &sctx->gsvs_ring, 0, sctx->gsvs_ring.buffer_size,
+                          false, false, 0, 0);
 }
 
 static void si_update_derived_state(struct si_context *sctx)
@@ -620,7 +623,8 @@ static void si_update_derived_state(struct si_context *sctx)
                        sctx->b.flags |= R600_CONTEXT_VGT_FLUSH;
                si_pm4_bind_state(sctx, gs_rings, sctx->gs_rings);
 
-               si_set_ring_buffer(ctx, PIPE_SHADER_GEOMETRY, 1, &sctx->gsvs_ring,
+               si_set_ring_buffer(ctx, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
+                                  &sctx->gsvs_ring,
                                   sctx->gs_shader->current->shader.gs_max_out_vertices *
                                   sctx->gs_shader->current->shader.noutput * 16,
                                   64, true, true, 4, 16);