* Christian König <christian.koenig@amd.com>
*/
-#include "util/u_memory.h"
-#include "util/u_framebuffer.h"
-#include "util/u_blitter.h"
-#include "tgsi/tgsi_parse.h"
#include "si_pipe.h"
#include "si_shader.h"
-#include "si_state.h"
#include "../radeon/r600_cs.h"
#include "sid.h"
+#include "util/u_blitter.h"
+#include "util/u_format.h"
+#include "util/u_index_modify.h"
+#include "util/u_memory.h"
+#include "util/u_upload_mgr.h"
+
/*
* Shaders
*/
+static void si_pipe_shader_es(struct pipe_context *ctx, struct si_pipe_shader *shader)
+{
+ struct si_context *sctx = (struct si_context *)ctx;
+ struct si_pm4_state *pm4;
+ unsigned num_sgprs, num_user_sgprs;
+ unsigned vgpr_comp_cnt;
+ uint64_t va;
+
+ si_pm4_delete_state(sctx, es, shader->pm4);
+ pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
+
+ if (pm4 == NULL)
+ return;
+
+ va = r600_resource_va(ctx->screen, (void *)shader->bo);
+ si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
+
+ vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
+
+ num_user_sgprs = SI_VS_NUM_USER_SGPR;
+ num_sgprs = shader->num_sgprs;
+ /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
+ if ((num_user_sgprs + 1) > num_sgprs) {
+ /* Last 2 reserved SGPRs are used for VCC */
+ num_sgprs = num_user_sgprs + 1 + 2;
+ }
+ assert(num_sgprs <= 104);
+
+ si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
+ si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
+ si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
+ S_00B328_VGPRS((shader->num_vgprs - 1) / 4) |
+ S_00B328_SGPRS((num_sgprs - 1) / 8) |
+ S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt));
+ si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
+ S_00B32C_USER_SGPR(num_user_sgprs));
+
+ sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
+}
+
+static void si_pipe_shader_gs(struct pipe_context *ctx, struct si_pipe_shader *shader)
+{
+ struct si_context *sctx = (struct si_context *)ctx;
+ unsigned gs_vert_itemsize = shader->shader.noutput * (16 >> 2);
+ unsigned gs_max_vert_out = shader->shader.gs_max_out_vertices;
+ unsigned gsvs_itemsize = gs_vert_itemsize * gs_max_vert_out;
+ unsigned cut_mode;
+ struct si_pm4_state *pm4;
+ unsigned num_sgprs, num_user_sgprs;
+ uint64_t va;
+
+ /* The GSVS_RING_ITEMSIZE register takes 15 bits */
+ assert(gsvs_itemsize < (1 << 15));
+
+ si_pm4_delete_state(sctx, gs, shader->pm4);
+ pm4 = shader->pm4 = si_pm4_alloc_state(sctx);
+
+ if (pm4 == NULL)
+ return;
+
+ if (gs_max_vert_out <= 128) {
+ cut_mode = V_028A40_GS_CUT_128;
+ } else if (gs_max_vert_out <= 256) {
+ cut_mode = V_028A40_GS_CUT_256;
+ } else if (gs_max_vert_out <= 512) {
+ cut_mode = V_028A40_GS_CUT_512;
+ } else {
+ assert(gs_max_vert_out <= 1024);
+ cut_mode = V_028A40_GS_CUT_1024;
+ }
+
+ si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
+ S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
+ S_028A40_CUT_MODE(cut_mode)|
+ S_028A40_ES_WRITE_OPTIMIZE(1) |
+ S_028A40_GS_WRITE_OPTIMIZE(1));
+
+ si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
+ si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize);
+ si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize);
+
+ si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
+ shader->shader.nparam * (16 >> 2));
+ si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
+
+ si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, gs_max_vert_out);
+
+ si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize);
+
+ va = r600_resource_va(ctx->screen, (void *)shader->bo);
+ si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
+ si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
+ si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
+
+ num_user_sgprs = SI_GS_NUM_USER_SGPR;
+ num_sgprs = shader->num_sgprs;
+ /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
+ if ((num_user_sgprs + 2) > num_sgprs) {
+ /* Last 2 reserved SGPRs are used for VCC */
+ num_sgprs = num_user_sgprs + 2 + 2;
+ }
+ assert(num_sgprs <= 104);
+
+ si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
+ S_00B228_VGPRS((shader->num_vgprs - 1) / 4) |
+ S_00B228_SGPRS((num_sgprs - 1) / 8));
+ si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
+ S_00B22C_USER_SGPR(num_user_sgprs));
+
+ sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
+}
+
static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader)
{
struct si_context *sctx = (struct si_context *)ctx;
if (pm4 == NULL)
return;
+ va = r600_resource_va(ctx->screen, (void *)shader->bo);
+ si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
+
+ vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
+
+ num_user_sgprs = SI_VS_NUM_USER_SGPR;
+ num_sgprs = shader->num_sgprs;
+ if (num_user_sgprs > num_sgprs) {
+ /* Last 2 reserved SGPRs are used for VCC */
+ num_sgprs = num_user_sgprs + 2;
+ }
+ assert(num_sgprs <= 104);
+
/* Certain attributes (position, psize, etc.) don't count as params.
* VS is required to export at least one param and r600_shader_from_tgsi()
* takes care of adding a dummy export.
V_02870C_SPI_SHADER_4COMP :
V_02870C_SPI_SHADER_NONE));
- va = r600_resource_va(ctx->screen, (void *)shader->bo);
- si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
-
- num_user_sgprs = SI_VS_NUM_USER_SGPR;
- num_sgprs = shader->num_sgprs;
- if (num_user_sgprs > num_sgprs) {
- /* Last 2 reserved SGPRs are used for VCC */
- num_sgprs = num_user_sgprs + 2;
- }
- assert(num_sgprs <= 104);
-
- vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
-
si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
S_00B128_SGPRS((num_sgprs - 1) / 8) |
S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
S_00B12C_SO_EN(!!shader->selector->so.num_outputs));
- si_pm4_bind_state(sctx, vs, shader->pm4);
sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
}
{
struct si_context *sctx = (struct si_context *)ctx;
struct si_pm4_state *pm4;
- unsigned i, exports_ps, spi_ps_in_control, db_shader_control;
+ unsigned i, spi_ps_in_control, db_shader_control;
unsigned num_sgprs, num_user_sgprs;
- unsigned spi_baryc_cntl = 0, spi_ps_input_ena, spi_shader_z_format;
+ unsigned spi_baryc_cntl = 0, spi_ps_input_ena;
uint64_t va;
si_pm4_delete_state(sctx, ps, shader->pm4);
return;
db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
- S_02880C_ALPHA_TO_MASK_DISABLE(sctx->fb_cb0_is_integer);
+ S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer);
for (i = 0; i < shader->shader.ninput; i++) {
switch (shader->shader.input[i].name) {
}
}
- for (i = 0; i < shader->shader.noutput; i++) {
- if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION)
- db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
- if (shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
- db_shader_control |= S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
- }
+ db_shader_control |= shader->db_shader_control;
+
if (shader->shader.uses_kill || shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
db_shader_control |= S_02880C_KILL_ENABLE(1);
- exports_ps = 0;
- for (i = 0; i < shader->shader.noutput; i++) {
- if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION ||
- shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
- exports_ps |= 1;
- }
- if (!exports_ps) {
- /* always at least export 1 component per pixel */
- exports_ps = 2;
- }
-
- spi_ps_in_control = S_0286D8_NUM_INTERP(shader->shader.ninterp) |
+ spi_ps_in_control = S_0286D8_NUM_INTERP(shader->shader.nparam) |
S_0286D8_BC_OPTIMIZE_DISABLE(1);
si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
- if (G_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(db_shader_control))
- spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
- else if (G_02880C_Z_EXPORT_ENABLE(db_shader_control))
- spi_shader_z_format = V_028710_SPI_SHADER_32_R;
- else
- spi_shader_z_format = 0;
- si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, spi_shader_z_format);
+ si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format);
si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
shader->spi_shader_col_format);
si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
va = r600_resource_va(ctx->screen, (void *)shader->bo);
- si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
+ si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
- shader->cb0_is_integer = sctx->fb_cb0_is_integer;
+ shader->cb0_is_integer = sctx->framebuffer.cb0_is_integer;
shader->sprite_coord_enable = sctx->sprite_coord_enable;
- si_pm4_bind_state(sctx, ps, shader->pm4);
sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
}
[PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
[PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
[PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
- [PIPE_PRIM_LINES_ADJACENCY] = ~0,
- [PIPE_PRIM_LINE_STRIP_ADJACENCY] = ~0,
- [PIPE_PRIM_TRIANGLES_ADJACENCY] = ~0,
- [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = ~0
+ [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
+ [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
+ [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
+ [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ
};
unsigned result = prim_conv[pprim];
if (result == ~0) {
const struct pipe_index_buffer *ib)
{
struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
- struct si_shader *vs = &sctx->vs_shader->current->shader;
+ struct si_shader *vs = si_get_vs_state(sctx);
unsigned prim = si_conv_pipe_prim(info->mode);
- unsigned gs_out_prim = si_conv_prim_to_gs_out(info->mode);
+ unsigned gs_out_prim =
+ si_conv_prim_to_gs_out(sctx->gs_shader ?
+ sctx->gs_shader->current->shader.gs_output_prim :
+ info->mode);
unsigned ls_mask = 0;
if (pm4 == NULL)
/* If the WD switch is false, the IA switch must be false too. */
bool ia_switch_on_eop = wd_switch_on_eop;
- si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
+ si_pm4_set_reg(pm4, R_028B74_VGT_DISPATCH_DRAW_INDEX,
+ ib->index_size == 4 ? 0xFC000000 : 0xFC00);
+
+ si_pm4_cmd_begin(pm4, PKT3_DRAW_PREAMBLE);
+ si_pm4_cmd_add(pm4, prim); /* VGT_PRIMITIVE_TYPE */
+ si_pm4_cmd_add(pm4, /* IA_MULTI_VGT_PARAM */
S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
S_028AA8_PARTIAL_VS_WAVE_ON(1) |
S_028AA8_PRIMGROUP_SIZE(63) |
S_028AA8_WD_SWITCH_ON_EOP(wd_switch_on_eop));
- si_pm4_set_reg(pm4, R_028B74_VGT_DISPATCH_DRAW_INDEX,
- ib->index_size == 4 ? 0xFC000000 : 0xFC00);
-
- si_pm4_set_reg(pm4, R_030908_VGT_PRIMITIVE_TYPE, prim);
+ si_pm4_cmd_add(pm4, 0); /* VGT_LS_HS_CONFIG */
+ si_pm4_cmd_end(pm4, false);
} else {
si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
}
info->indexed ? info->index_bias : info->start);
si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
- si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 + SI_SGPR_START_INSTANCE * 4,
+ si_pm4_set_reg(pm4, SI_SGPR_START_INSTANCE * 4 +
+ (sctx->gs_shader ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
+ R_00B130_SPI_SHADER_USER_DATA_VS_0),
info->start_instance);
if (prim == V_008958_DI_PT_LINELIST)
static void si_update_spi_map(struct si_context *sctx)
{
struct si_shader *ps = &sctx->ps_shader->current->shader;
- struct si_shader *vs = &sctx->vs_shader->current->shader;
+ struct si_shader *vs = si_get_vs_state(sctx);
struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
unsigned i, j, tmp;
si_pm4_set_state(sctx, spi, pm4);
}
+/* Initialize state related to ESGS / GSVS ring buffers */
+static void si_init_gs_rings(struct si_context *sctx)
+{
+ unsigned size = 128 * 1024;
+
+ assert(!sctx->gs_rings);
+ sctx->gs_rings = si_pm4_alloc_state(sctx);
+
+ sctx->esgs_ring.buffer =
+ pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
+ PIPE_USAGE_DEFAULT, size);
+ sctx->esgs_ring.buffer_size = size;
+
+ size = 64 * 1024 * 1024;
+ sctx->gsvs_ring.buffer =
+ pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
+ PIPE_USAGE_DEFAULT, size);
+ sctx->gsvs_ring.buffer_size = size;
+
+ if (sctx->b.chip_class >= CIK) {
+ si_pm4_set_reg(sctx->gs_rings, R_030900_VGT_ESGS_RING_SIZE,
+ sctx->esgs_ring.buffer_size / 256);
+ si_pm4_set_reg(sctx->gs_rings, R_030904_VGT_GSVS_RING_SIZE,
+ sctx->gsvs_ring.buffer_size / 256);
+ } else {
+ si_pm4_set_reg(sctx->gs_rings, R_0088C8_VGT_ESGS_RING_SIZE,
+ sctx->esgs_ring.buffer_size / 256);
+ si_pm4_set_reg(sctx->gs_rings, R_0088CC_VGT_GSVS_RING_SIZE,
+ sctx->gsvs_ring.buffer_size / 256);
+ }
+
+ si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
+ &sctx->esgs_ring, 0, sctx->esgs_ring.buffer_size,
+ true, true, 4, 64);
+ si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
+ &sctx->esgs_ring, 0, sctx->esgs_ring.buffer_size,
+ false, false, 0, 0);
+ si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
+ &sctx->gsvs_ring, 0, sctx->gsvs_ring.buffer_size,
+ false, false, 0, 0);
+}
+
static void si_update_derived_state(struct si_context *sctx)
{
struct pipe_context * ctx = (struct pipe_context*)sctx;
- unsigned vs_dirty = 0, ps_dirty = 0;
if (!sctx->blitter->running) {
/* Flush depth textures which need to be flushed. */
}
}
- si_shader_select(ctx, sctx->vs_shader, &vs_dirty);
+ if (sctx->gs_shader) {
+ si_shader_select(ctx, sctx->gs_shader);
- if (!sctx->vs_shader->current->pm4) {
- si_pipe_shader_vs(ctx, sctx->vs_shader->current);
- vs_dirty = 0;
- }
+ if (!sctx->gs_shader->current->pm4) {
+ si_pipe_shader_gs(ctx, sctx->gs_shader->current);
+ si_pipe_shader_vs(ctx,
+ sctx->gs_shader->current->gs_copy_shader);
+ }
+
+ si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
+ si_pm4_bind_state(sctx, vs, sctx->gs_shader->current->gs_copy_shader->pm4);
+
+ sctx->b.streamout.stride_in_dw = sctx->gs_shader->so.stride;
+
+ si_shader_select(ctx, sctx->vs_shader);
+
+ if (!sctx->vs_shader->current->pm4)
+ si_pipe_shader_es(ctx, sctx->vs_shader->current);
+
+ si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4);
+
+ if (!sctx->gs_rings)
+ si_init_gs_rings(sctx);
+ if (sctx->emitted.named.gs_rings != sctx->gs_rings)
+ sctx->b.flags |= R600_CONTEXT_VGT_FLUSH;
+ si_pm4_bind_state(sctx, gs_rings, sctx->gs_rings);
+
+ si_set_ring_buffer(ctx, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
+ &sctx->gsvs_ring,
+ sctx->gs_shader->current->shader.gs_max_out_vertices *
+ sctx->gs_shader->current->shader.noutput * 16,
+ 64, true, true, 4, 16);
+
+ if (!sctx->gs_on) {
+ sctx->gs_on = si_pm4_alloc_state(sctx);
+
+ si_pm4_set_reg(sctx->gs_on, R_028B54_VGT_SHADER_STAGES_EN,
+ S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
+ S_028B54_GS_EN(1) |
+ S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER));
+ }
+ si_pm4_bind_state(sctx, gs_onoff, sctx->gs_on);
+ } else {
+ si_shader_select(ctx, sctx->vs_shader);
+
+ if (!sctx->vs_shader->current->pm4)
+ si_pipe_shader_vs(ctx, sctx->vs_shader->current);
- if (vs_dirty) {
si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
- }
+ sctx->b.streamout.stride_in_dw = sctx->vs_shader->so.stride;
- si_shader_select(ctx, sctx->ps_shader, &ps_dirty);
+ if (!sctx->gs_off) {
+ sctx->gs_off = si_pm4_alloc_state(sctx);
- if (!sctx->ps_shader->current->pm4) {
- si_pipe_shader_ps(ctx, sctx->ps_shader->current);
- ps_dirty = 0;
+ si_pm4_set_reg(sctx->gs_off, R_028A40_VGT_GS_MODE, 0);
+ si_pm4_set_reg(sctx->gs_off, R_028B54_VGT_SHADER_STAGES_EN, 0);
+ }
+ si_pm4_bind_state(sctx, gs_onoff, sctx->gs_off);
+ si_pm4_bind_state(sctx, gs_rings, NULL);
+ si_pm4_bind_state(sctx, gs, NULL);
+ si_pm4_bind_state(sctx, es, NULL);
}
- if (sctx->ps_shader->current->cb0_is_integer != sctx->fb_cb0_is_integer) {
+
+ si_shader_select(ctx, sctx->ps_shader);
+
+ if (!sctx->ps_shader->current->pm4 ||
+ sctx->ps_shader->current->cb0_is_integer != sctx->framebuffer.cb0_is_integer)
si_pipe_shader_ps(ctx, sctx->ps_shader->current);
- ps_dirty = 0;
- }
- if (ps_dirty) {
- si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
- }
+ si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs)) {
/* XXX: Emitting the PS state even when only the VS changed
si_pm4_sh_data_add(pm4, sctx->vertex_elements->rsrc_word3[i]);
if (!bound[ve->vertex_buffer_index]) {
- si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
+ si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ,
+ RADEON_PRIO_SHADER_BUFFER_RO);
bound[ve->vertex_buffer_index] = true;
}
}
- si_pm4_sh_data_end(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, SI_SGPR_VERTEX_BUFFER);
+ si_pm4_sh_data_end(pm4, sctx->gs_shader ?
+ R_00B330_SPI_SHADER_USER_DATA_ES_0 :
+ R_00B130_SPI_SHADER_USER_DATA_VS_0,
+ SI_SGPR_VERTEX_BUFFER);
si_pm4_set_state(sctx, vertex_buffers, pm4);
}
/* queries need some special values
* (this is non-zero if any query is active) */
- if (sctx->num_cs_dw_nontimer_queries_suspend) {
+ if (sctx->b.num_occlusion_queries > 0) {
if (sctx->b.chip_class >= CIK) {
si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
S_028004_PERFECT_ZPASS_COUNTS(1) |
- S_028004_SAMPLE_RATE(sctx->fb_log_samples) |
+ S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
S_028004_ZPASS_ENABLE(1) |
S_028004_SLICE_EVEN_ENABLE(1) |
S_028004_SLICE_ODD_ENABLE(1));
} else {
si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
S_028004_PERFECT_ZPASS_COUNTS(1) |
- S_028004_SAMPLE_RATE(sctx->fb_log_samples));
+ S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
}
}
si_pm4_cmd_add(pm4, va >> 32UL); /* src address hi */
si_pm4_cmd_add(pm4, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
si_pm4_cmd_add(pm4, 0); /* unused */
- si_pm4_add_bo(pm4, t->buf_filled_size, RADEON_USAGE_READ);
+ si_pm4_add_bo(pm4, t->buf_filled_size, RADEON_USAGE_READ,
+ RADEON_PRIO_MIN);
si_pm4_cmd_end(pm4, true);
}
si_pm4_cmd_add(pm4, V_028A7C_VGT_INDEX_16 | (SI_BIG_ENDIAN ?
V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
}
- si_pm4_cmd_end(pm4, sctx->predicate_drawing);
+ si_pm4_cmd_end(pm4, sctx->b.predicate_drawing);
si_pm4_cmd_begin(pm4, PKT3_NUM_INSTANCES);
si_pm4_cmd_add(pm4, info->instance_count);
- si_pm4_cmd_end(pm4, sctx->predicate_drawing);
+ si_pm4_cmd_end(pm4, sctx->b.predicate_drawing);
if (info->indexed) {
uint32_t max_size = (ib->buffer->width0 - ib->offset) /
va = r600_resource_va(&sctx->screen->b.b, ib->buffer);
va += ib->offset;
- si_pm4_add_bo(pm4, (struct r600_resource *)ib->buffer, RADEON_USAGE_READ);
+ si_pm4_add_bo(pm4, (struct r600_resource *)ib->buffer, RADEON_USAGE_READ,
+ RADEON_PRIO_MIN);
si_cmd_draw_index_2(pm4, max_size, va, info->count,
V_0287F0_DI_SRC_SEL_DMA,
- sctx->predicate_drawing);
+ sctx->b.predicate_drawing);
} else {
uint32_t initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
initiator |= S_0287F0_USE_OPAQUE(!!info->count_from_stream_output);
- si_cmd_draw_index_auto(pm4, info->count, initiator, sctx->predicate_drawing);
+ si_cmd_draw_index_auto(pm4, info->count, initiator, sctx->b.predicate_drawing);
}
si_pm4_set_state(sctx, draw, pm4);
radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
}
+ if (sctx->flags & R600_CONTEXT_VGT_FLUSH) {
+ radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
+ radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
+ }
+
sctx->flags = 0;
}
ib.offset = sctx->index_buffer.offset + info->start * ib.index_size;
/* Translate or upload, if needed. */
- si_translate_index_buffer(sctx, &ib, info->count);
+ if (ib.index_size == 1) {
+ struct pipe_resource *out_buffer = NULL;
+ unsigned out_offset;
+ void *ptr;
+
+ u_upload_alloc(sctx->b.uploader, 0, info->count * 2,
+ &out_offset, &out_buffer, &ptr);
+
+ util_shorten_ubyte_elts_to_userptr(
+ &sctx->b.b, &ib, 0, ib.offset, info->count, ptr);
+
+ pipe_resource_reference(&ib.buffer, NULL);
+ ib.user_buffer = NULL;
+ ib.buffer = out_buffer;
+ ib.offset = out_offset;
+ ib.index_size = 2;
+ }
if (ib.user_buffer && !ib.buffer) {
- si_upload_index_buffer(sctx, &ib, info->count);
+ u_upload_data(sctx->b.uploader, 0, info->count * ib.index_size,
+ ib.user_buffer, &ib.offset, &ib.buffer);
}
}
/* Check flush flags. */
if (sctx->b.flags)
- sctx->atoms.cache_flush->dirty = true;
+ sctx->atoms.s.cache_flush->dirty = true;
si_need_cs_space(sctx, 0, TRUE);
sctx->pm4_dirty_cdwords = 0;
#if SI_TRACE_CS
- if (sctx->screen->trace_bo) {
+ if (sctx->screen->b.trace_bo) {
si_trace_emit(sctx);
}
#endif
/* Set the depth buffer as dirty. */
- if (sctx->framebuffer.zsbuf) {
- struct pipe_surface *surf = sctx->framebuffer.zsbuf;
+ if (sctx->framebuffer.state.zsbuf) {
+ struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
struct r600_texture *rtex = (struct r600_texture *)surf->texture;
rtex->dirty_level_mask |= 1 << surf->u.tex.level;
}
- if (sctx->fb_compressed_cb_mask) {
+ if (sctx->framebuffer.compressed_cb_mask) {
struct pipe_surface *surf;
struct r600_texture *rtex;
- unsigned mask = sctx->fb_compressed_cb_mask;
+ unsigned mask = sctx->framebuffer.compressed_cb_mask;
do {
unsigned i = u_bit_scan(&mask);
- surf = sctx->framebuffer.cbufs[i];
+ surf = sctx->framebuffer.state.cbufs[i];
rtex = (struct r600_texture*)surf->texture;
rtex->dirty_level_mask |= 1 << surf->u.tex.level;
}
pipe_resource_reference(&ib.buffer, NULL);
+ sctx->b.num_draw_calls++;
}
projects / mesa.git / blobdiff