return;
va = r600_resource_va(ctx->screen, (void *)shader->bo);
- si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
+ si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize);
va = r600_resource_va(ctx->screen, (void *)shader->bo);
- si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
+ si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
return;
va = r600_resource_va(ctx->screen, (void *)shader->bo);
- si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
+ si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
vgpr_comp_cnt = shader->shader.uses_instanceid ? 3 : 0;
{
struct si_context *sctx = (struct si_context *)ctx;
struct si_pm4_state *pm4;
- unsigned i, exports_ps, spi_ps_in_control, db_shader_control;
+ unsigned i, spi_ps_in_control, db_shader_control;
unsigned num_sgprs, num_user_sgprs;
- unsigned spi_baryc_cntl = 0, spi_ps_input_ena, spi_shader_z_format;
+ unsigned spi_baryc_cntl = 0, spi_ps_input_ena;
uint64_t va;
si_pm4_delete_state(sctx, ps, shader->pm4);
return;
db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
- S_02880C_ALPHA_TO_MASK_DISABLE(sctx->fb_cb0_is_integer);
+ S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer);
for (i = 0; i < shader->shader.ninput; i++) {
switch (shader->shader.input[i].name) {
}
}
- for (i = 0; i < shader->shader.noutput; i++) {
- if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION)
- db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
- if (shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
- db_shader_control |= S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
- }
+ db_shader_control |= shader->db_shader_control;
+
if (shader->shader.uses_kill || shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
db_shader_control |= S_02880C_KILL_ENABLE(1);
- exports_ps = 0;
- for (i = 0; i < shader->shader.noutput; i++) {
- if (shader->shader.output[i].name == TGSI_SEMANTIC_POSITION ||
- shader->shader.output[i].name == TGSI_SEMANTIC_STENCIL)
- exports_ps |= 1;
- }
- if (!exports_ps) {
- /* always at least export 1 component per pixel */
- exports_ps = 2;
- }
-
spi_ps_in_control = S_0286D8_NUM_INTERP(shader->shader.nparam) |
S_0286D8_BC_OPTIMIZE_DISABLE(1);
si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
- if (G_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(db_shader_control))
- spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
- else if (G_02880C_Z_EXPORT_ENABLE(db_shader_control))
- spi_shader_z_format = V_028710_SPI_SHADER_32_R;
- else
- spi_shader_z_format = 0;
- si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, spi_shader_z_format);
+ si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format);
si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
shader->spi_shader_col_format);
si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
va = r600_resource_va(ctx->screen, (void *)shader->bo);
- si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ);
+ si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
- shader->cb0_is_integer = sctx->fb_cb0_is_integer;
+ shader->cb0_is_integer = sctx->framebuffer.cb0_is_integer;
shader->sprite_coord_enable = sctx->sprite_coord_enable;
sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
}
/* If the WD switch is false, the IA switch must be false too. */
bool ia_switch_on_eop = wd_switch_on_eop;
- si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
+ si_pm4_set_reg(pm4, R_028B74_VGT_DISPATCH_DRAW_INDEX,
+ ib->index_size == 4 ? 0xFC000000 : 0xFC00);
+
+ si_pm4_cmd_begin(pm4, PKT3_DRAW_PREAMBLE);
+ si_pm4_cmd_add(pm4, prim); /* VGT_PRIMITIVE_TYPE */
+ si_pm4_cmd_add(pm4, /* IA_MULTI_VGT_PARAM */
S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
S_028AA8_PARTIAL_VS_WAVE_ON(1) |
S_028AA8_PRIMGROUP_SIZE(63) |
S_028AA8_WD_SWITCH_ON_EOP(wd_switch_on_eop));
- si_pm4_set_reg(pm4, R_028B74_VGT_DISPATCH_DRAW_INDEX,
- ib->index_size == 4 ? 0xFC000000 : 0xFC00);
-
- si_pm4_set_reg(pm4, R_030908_VGT_PRIMITIVE_TYPE, prim);
+ si_pm4_cmd_add(pm4, 0); /* VGT_LS_HS_CONFIG */
+ si_pm4_cmd_end(pm4, false);
} else {
si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
}
sctx->esgs_ring.buffer =
pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
- PIPE_USAGE_STATIC, size);
+ PIPE_USAGE_DEFAULT, size);
sctx->esgs_ring.buffer_size = size;
size = 64 * 1024 * 1024;
sctx->gsvs_ring.buffer =
pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
- PIPE_USAGE_STATIC, size);
+ PIPE_USAGE_DEFAULT, size);
sctx->gsvs_ring.buffer_size = size;
if (sctx->b.chip_class >= CIK) {
si_shader_select(ctx, sctx->ps_shader);
if (!sctx->ps_shader->current->pm4 ||
- sctx->ps_shader->current->cb0_is_integer != sctx->fb_cb0_is_integer)
+ sctx->ps_shader->current->cb0_is_integer != sctx->framebuffer.cb0_is_integer)
si_pipe_shader_ps(ctx, sctx->ps_shader->current);
si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
si_pm4_sh_data_add(pm4, sctx->vertex_elements->rsrc_word3[i]);
if (!bound[ve->vertex_buffer_index]) {
- si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
+ si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ,
+ RADEON_PRIO_SHADER_BUFFER_RO);
bound[ve->vertex_buffer_index] = true;
}
}
if (sctx->b.chip_class >= CIK) {
si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
S_028004_PERFECT_ZPASS_COUNTS(1) |
- S_028004_SAMPLE_RATE(sctx->fb_log_samples) |
+ S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
S_028004_ZPASS_ENABLE(1) |
S_028004_SLICE_EVEN_ENABLE(1) |
S_028004_SLICE_ODD_ENABLE(1));
} else {
si_pm4_set_reg(pm4, R_028004_DB_COUNT_CONTROL,
S_028004_PERFECT_ZPASS_COUNTS(1) |
- S_028004_SAMPLE_RATE(sctx->fb_log_samples));
+ S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
}
}
si_pm4_cmd_add(pm4, va >> 32UL); /* src address hi */
si_pm4_cmd_add(pm4, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
si_pm4_cmd_add(pm4, 0); /* unused */
- si_pm4_add_bo(pm4, t->buf_filled_size, RADEON_USAGE_READ);
+ si_pm4_add_bo(pm4, t->buf_filled_size, RADEON_USAGE_READ,
+ RADEON_PRIO_MIN);
si_pm4_cmd_end(pm4, true);
}
va = r600_resource_va(&sctx->screen->b.b, ib->buffer);
va += ib->offset;
- si_pm4_add_bo(pm4, (struct r600_resource *)ib->buffer, RADEON_USAGE_READ);
+ si_pm4_add_bo(pm4, (struct r600_resource *)ib->buffer, RADEON_USAGE_READ,
+ RADEON_PRIO_MIN);
si_cmd_draw_index_2(pm4, max_size, va, info->count,
V_0287F0_DI_SRC_SEL_DMA,
sctx->b.predicate_drawing);
/* Check flush flags. */
if (sctx->b.flags)
- sctx->atoms.cache_flush->dirty = true;
+ sctx->atoms.s.cache_flush->dirty = true;
si_need_cs_space(sctx, 0, TRUE);
#endif
/* Set the depth buffer as dirty. */
- if (sctx->framebuffer.zsbuf) {
- struct pipe_surface *surf = sctx->framebuffer.zsbuf;
+ if (sctx->framebuffer.state.zsbuf) {
+ struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
struct r600_texture *rtex = (struct r600_texture *)surf->texture;
rtex->dirty_level_mask |= 1 << surf->u.tex.level;
}
- if (sctx->fb_compressed_cb_mask) {
+ if (sctx->framebuffer.compressed_cb_mask) {
struct pipe_surface *surf;
struct r600_texture *rtex;
- unsigned mask = sctx->fb_compressed_cb_mask;
+ unsigned mask = sctx->framebuffer.compressed_cb_mask;
do {
unsigned i = u_bit_scan(&mask);
- surf = sctx->framebuffer.cbufs[i];
+ surf = sctx->framebuffer.state.cbufs[i];
rtex = (struct r600_texture*)surf->texture;
rtex->dirty_level_mask |= 1 << surf->u.tex.level;