radeonsi: remove si_atom::id

[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index f8d52cbc98f275859022cecece3cfe569be86f86..8d41988e382a9abbe7cef47151b4214e52ab0e7f 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -362,7 +362,8 @@ si_get_init_multi_vgt_param(struct si_screen *sscreen,
                                    sscreen->info.family == CHIP_FIJI ||
                                    sscreen->info.family == CHIP_POLARIS10 ||
                                    sscreen->info.family == CHIP_POLARIS11 ||
-                                   sscreen->info.family == CHIP_POLARIS12)
+                                   sscreen->info.family == CHIP_POLARIS12 ||
+                                   sscreen->info.family == CHIP_VEGAM)
                                        partial_vs_wave = true;
                        } else {
                                partial_vs_wave = true;
@@ -1181,7 +1182,7 @@ static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_i
        /* Emit state atoms. */
        unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
        while (mask) {
-               struct r600_atom *atom = sctx->atoms.array[u_bit_scan(&mask)];
+               struct si_atom *atom = &sctx->atoms.array[u_bit_scan(&mask)];
 
                atom->emit(sctx, atom);
        }
@@ -1255,7 +1256,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
                sctx->framebuffer.dirty_cbufs |=
                        ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
                sctx->framebuffer.dirty_zsbuf = true;
-               si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
+               si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
                si_update_all_texture_descriptors(sctx);
        }
 
@@ -1281,7 +1282,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
                bool new_is_poly = rast_prim >= PIPE_PRIM_TRIANGLES;
                if (old_is_poly != new_is_poly) {
                        sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
-                       si_mark_atom_dirty(sctx, &sctx->scissors.atom);
+                       si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
                }
 
                sctx->current_rast_prim = rast_prim;
@@ -1417,7 +1418,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
         * more involved alternative workaround.
         */
        if ((sctx->family == CHIP_VEGA10 || sctx->family == CHIP_RAVEN) &&
-           si_is_atom_dirty(sctx, &sctx->scissors.atom)) {
+           si_is_atom_dirty(sctx, &sctx->atoms.s.scissors)) {
                sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
                si_emit_cache_flush(sctx);
        }
@@ -1435,7 +1436,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
                unsigned masked_atoms = 0;
 
                if (unlikely(sctx->flags & SI_CONTEXT_FLUSH_FOR_RENDER_COND))
-                       masked_atoms |= 1u << sctx->render_cond_atom.id;
+                       masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.render_cond);
 
                if (!si_upload_graphics_shader_descriptors(sctx))
                        return;
@@ -1445,8 +1446,8 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
                si_emit_cache_flush(sctx);
                /* <-- CUs are idle here. */
 
-               if (si_is_atom_dirty(sctx, &sctx->render_cond_atom))
-                       sctx->render_cond_atom.emit(sctx, NULL);
+               if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond))
+                       sctx->atoms.s.render_cond.emit(sctx, NULL);
                sctx->dirty_atoms = 0;
 
                si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
@@ -1456,7 +1457,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
                 * in parallel, but starting the draw first is more important.
                 */
                if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask)
-                       cik_emit_prefetch_L2(sctx);
+                       cik_emit_prefetch_L2(sctx, false);
        } else {
                /* If we don't wait for idle, start prefetches first, then set
                 * states, and draw at the end.
@@ -1464,14 +1465,20 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
                if (sctx->flags)
                        si_emit_cache_flush(sctx);
 
+               /* Only prefetch the API VS and VBO descriptors. */
                if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask)
-                       cik_emit_prefetch_L2(sctx);
+                       cik_emit_prefetch_L2(sctx, true);
 
                if (!si_upload_graphics_shader_descriptors(sctx))
                        return;
 
                si_emit_all_states(sctx, info, 0);
                si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);
+
+               /* Prefetch the remaining shaders after the draw has been
+                * started. */
+               if (sctx->chip_class >= CIK && sctx->prefetch_L2_mask)
+                       cik_emit_prefetch_L2(sctx, false);
        }
 
        if (unlikely(sctx->current_saved_cs)) {