radeonsi: don't use WRITE_DATA.DST_SEL == MEM_GRBM on >= CIK

[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index d011adb2cad37e25d67a5f3dc50efdd9eea8c851..9a80bd813272f36068affdb1e5b4b0957beb121a 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -315,10 +315,12 @@ static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
        switch (info->mode) {
        case PIPE_PRIM_PATCHES:
                return info->count / info->vertices_per_patch;
+       case PIPE_PRIM_POLYGON:
+               return info->count >= 3;
        case SI_PRIM_RECTANGLE_LIST:
                return info->count / 3;
        default:
-               return u_prims_for_vertices(info->mode, info->count);
+               return u_decomposed_prims_for_vertices(info->mode, info->count);
        }
 }
 
@@ -348,20 +350,11 @@ si_get_init_multi_vgt_param(struct si_screen *sscreen,
                    key->u.uses_gs)
                        partial_vs_wave = true;
 
-               /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
+               /* Needed for 028B6C_DISTRIBUTION_MODE != 0. (implies >= VI) */
                if (sscreen->has_distributed_tess) {
                        if (key->u.uses_gs) {
-                               if (sscreen->info.chip_class <= VI)
+                               if (sscreen->info.chip_class == VI)
                                        partial_es_wave = true;
-
-                               /* GPU hang workaround. */
-                               if (sscreen->info.family == CHIP_TONGA ||
-                                   sscreen->info.family == CHIP_FIJI ||
-                                   sscreen->info.family == CHIP_POLARIS10 ||
-                                   sscreen->info.family == CHIP_POLARIS11 ||
-                                   sscreen->info.family == CHIP_POLARIS12 ||
-                                   sscreen->info.family == CHIP_VEGAM)
-                                       partial_vs_wave = true;
                        } else {
                                partial_vs_wave = true;
                        }
@@ -417,6 +410,18 @@ si_get_init_multi_vgt_param(struct si_screen *sscreen,
                if (sscreen->info.max_se == 4 && !wd_switch_on_eop)
                        ia_switch_on_eoi = true;
 
+               /* HW engineers suggested that PARTIAL_VS_WAVE_ON should be set
+                * to work around a GS hang.
+                */
+               if (key->u.uses_gs &&
+                   (sscreen->info.family == CHIP_TONGA ||
+                    sscreen->info.family == CHIP_FIJI ||
+                    sscreen->info.family == CHIP_POLARIS10 ||
+                    sscreen->info.family == CHIP_POLARIS11 ||
+                    sscreen->info.family == CHIP_POLARIS12 ||
+                    sscreen->info.family == CHIP_VEGAM))
+                       partial_vs_wave = true;
+
                /* Required by Hawaii and, for some special cases, by VI. */
                if (ia_switch_on_eoi &&
                    (sscreen->info.family == CHIP_HAWAII ||
@@ -813,10 +818,15 @@ static void si_emit_draw_packets(struct si_context *sctx,
                        radeon_emit(cs, di_src_sel);
                }
        } else {
+               unsigned instance_count = info->instance_count;
                int base_vertex;
 
-               radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
-               radeon_emit(cs, info->instance_count);
+               if (sctx->last_instance_count == SI_INSTANCE_COUNT_UNKNOWN ||
+                   sctx->last_instance_count != instance_count) {
+                       radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
+                       radeon_emit(cs, instance_count);
+                       sctx->last_instance_count = instance_count;
+               }
 
                /* Base vertex and start instance. */
                base_vertex = index_size ? info->index_bias : info->start;
@@ -1051,7 +1061,8 @@ void si_emit_cache_flush(struct si_context *sctx)
                                  EOP_DATA_SEL_VALUE_32BIT,
                                  sctx->wait_mem_scratch, va,
                                  sctx->wait_mem_number, SI_NOT_QUERY);
-               si_cp_wait_mem(sctx, va, sctx->wait_mem_number, 0xffffffff, 0);
+               si_cp_wait_mem(sctx, cs, va, sctx->wait_mem_number, 0xffffffff,
+                              WAIT_REG_MEM_EQUAL);
        }
 
        /* Make sure ME is idle (it executes most packets) before continuing.
@@ -1585,7 +1596,8 @@ void si_trace_emit(struct si_context *sctx)
        uint32_t trace_id = ++sctx->current_saved_cs->trace_id;
 
        radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
-       radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
+       radeon_emit(cs, S_370_DST_SEL(sctx->chip_class >= CIK ? V_370_MEM
+                                                             : V_370_MEM_GRBM) |
                    S_370_WR_CONFIRM(1) |
                    S_370_ENGINE_SEL(V_370_ME));
        radeon_emit(cs, va);