radeonsi/gfx9: prevent a GPU hang after a timestamp event

[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 23e9778fa5473e20a4722c8ba1bf76eae85d61f3..abe2b5cc658aaa9d3c4cdccc9824c622f255f1ac 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -894,7 +894,7 @@ void si_emit_cache_flush(struct si_context *sctx)
                        /* Necessary for DCC */
                        if (rctx->chip_class == VI)
                                r600_gfx_write_event_eop(rctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
-                                                        0, 0, NULL, 0, 0, 0);
+                                                        0, 0, NULL, 0, 0, 0, 0);
                }
                if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB)
                        cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
@@ -996,7 +996,7 @@ void si_emit_cache_flush(struct si_context *sctx)
                r600_gfx_write_event_eop(rctx, cb_db_event, tc_flags, 1,
                                         sctx->wait_mem_scratch, va,
                                         sctx->wait_mem_number - 1,
-                                        sctx->wait_mem_number);
+                                        sctx->wait_mem_number, 0);
                r600_gfx_wait_fence(rctx, va, sctx->wait_mem_number, 0xffffffff);
        }
 
@@ -1368,11 +1368,15 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
        if (!si_upload_vertex_buffer_descriptors(sctx))
                return;
 
-       /* GFX9 scissor bug workaround. There is also a more efficient but
-        * more involved alternative workaround. */
+       /* GFX9 scissor bug workaround. This must be done before VPORT scissor
+        * registers are changed. There is also a more efficient but more
+        * involved alternative workaround.
+        */
        if (sctx->b.chip_class == GFX9 &&
-           si_is_atom_dirty(sctx, &sctx->b.scissors.atom))
+           si_is_atom_dirty(sctx, &sctx->b.scissors.atom)) {
                sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
+               si_emit_cache_flush(sctx);
+       }
 
        /* Use optimal packet order based on whether we need to sync the pipeline. */
        if (unlikely(sctx->b.flags & (SI_CONTEXT_FLUSH_AND_INV_CB |