radeonsi: flush TC L2 cache for indirect draw data

[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index a60723d225d1e083f3d6bb5e5c7ca618823afaaf..b55930641315c8533e69eb0e699d8ffc0de35277 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -967,6 +967,11 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
                r600_resource(ib.buffer)->TC_L2_dirty = false;
        }
 
+       if (info->indirect && r600_resource(info->indirect)->TC_L2_dirty) {
+               sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
+               r600_resource(info->indirect)->TC_L2_dirty = false;
+       }
+
        /* Check flush flags. */
        if (sctx->b.flags)
                si_mark_atom_dirty(sctx, sctx->atoms.s.cache_flush);