radeonsi: Set PIPE_SHADER_CAP_MAX_SHADER_IMAGES

[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index a6753a7a528b12b678ca3402d7988b98e9a7f429..02489583423d10f3239fc41f9f5750da20d52e35 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -789,6 +789,23 @@ static void si_shader_ps(struct si_shader *shader)
                       S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
                       S_00B02C_USER_SGPR(num_user_sgprs) |
                       S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
+
+       /* Prefer RE_Z if the shader is complex enough. The requirement is either:
+        * - the shader uses at least 2 VMEM instructions, or
+        * - the code size is at least 50 2-dword instructions or 100 1-dword
+        *   instructions.
+        *
+        * Shaders with side effects that must execute independently of the
+        * depth test require LATE_Z.
+        */
+       if (info->writes_memory &&
+           !info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL])
+               shader->z_order = V_02880C_LATE_Z;
+       else if (info->num_memory_instructions >= 2 ||
+                shader->binary.code_size > 100*4)
+               shader->z_order = V_02880C_EARLY_Z_THEN_RE_Z;
+       else
+               shader->z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
 }
 
 static void si_shader_init_pm4_state(struct si_shader *shader)
@@ -1031,6 +1048,31 @@ static int si_shader_select(struct pipe_context *ctx,
        return si_shader_select_with_key(ctx, state, &key);
 }
 
+static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
+                                         union si_shader_key *key)
+{
+       unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
+
+       switch (info->processor) {
+       case TGSI_PROCESSOR_VERTEX:
+               switch (next_shader) {
+               case TGSI_PROCESSOR_GEOMETRY:
+                       key->vs.as_es = 1;
+                       break;
+               case TGSI_PROCESSOR_TESS_CTRL:
+               case TGSI_PROCESSOR_TESS_EVAL:
+                       key->vs.as_ls = 1;
+                       break;
+               }
+               break;
+
+       case TGSI_PROCESSOR_TESS_EVAL:
+               if (next_shader == TGSI_PROCESSOR_GEOMETRY)
+                       key->tes.as_es = 1;
+               break;
+       }
+}
+
 static void *si_create_shader_selector(struct pipe_context *ctx,
                                       const struct pipe_shader_state *state)
 {
@@ -1143,6 +1185,13 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
                break;
        }
 
+       if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL])
+               sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1);
+
+       if (sel->info.writes_memory)
+               sel->db_shader_control |= S_02880C_EXEC_ON_HIER_FAIL(1) |
+                                         S_02880C_EXEC_ON_NOOP(1);
+
        /* Compile the main shader part for use with a prolog and/or epilog. */
        if (sel->type != PIPE_SHADER_GEOMETRY &&
            !sscreen->use_monolithic_shaders) {
@@ -1153,6 +1202,7 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
                        goto error;
 
                shader->selector = sel;
+               si_parse_next_shader_property(&sel->info, &shader->key);
 
                tgsi_binary = si_get_tgsi_binary(sel);
 
@@ -1188,6 +1238,7 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
                union si_shader_key key;
 
                memset(&key, 0, sizeof(key));
+               si_parse_next_shader_property(&sel->info, &key);
 
                /* Set reasonable defaults, so that the shader key doesn't
                 * cause any code to be eliminated.
@@ -1985,15 +2036,18 @@ bool si_update_shaders(struct si_context *sctx)
        si_update_vgt_shader_config(sctx);
 
        if (sctx->ps_shader.cso) {
-               unsigned db_shader_control =
-                       sctx->ps_shader.cso->db_shader_control |
-                       S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
+               unsigned db_shader_control;
 
                r = si_shader_select(ctx, &sctx->ps_shader);
                if (r)
                        return false;
                si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
 
+               db_shader_control =
+                       sctx->ps_shader.cso->db_shader_control |
+                       S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS) |
+                       S_02880C_Z_ORDER(sctx->ps_shader.current->z_order);
+
                if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
                    sctx->sprite_coord_enable != rs->sprite_coord_enable ||
                    sctx->flatshade != rs->flatshade) {