radeonsi: move tessellation ring info into si_screen

[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 357c75aa370ce866aee2e7aa09f214d6eb40b03e..0d1dba15b8bd98631429b750c8b181288675518f 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -2970,50 +2970,25 @@ static bool si_update_spi_tmpring_size(struct si_context *sctx)
 
 static void si_init_tess_factor_ring(struct si_context *sctx)
 {
-       bool double_offchip_buffers = sctx->b.chip_class >= CIK &&
-                                     sctx->b.family != CHIP_CARRIZO &&
-                                     sctx->b.family != CHIP_STONEY;
-       /* This must be one less than the maximum number due to a hw limitation.
-        * Various hardware bugs in SI, CIK, and GFX9 need this.
-        */
-       unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
-       unsigned max_offchip_buffers = max_offchip_buffers_per_se *
-                                      sctx->screen->info.max_se;
-       unsigned offchip_granularity;
-
-       switch (sctx->screen->tess_offchip_block_dw_size) {
-       default:
-               assert(0);
-               /* fall through */
-       case 8192:
-               offchip_granularity = V_03093C_X_8K_DWORDS;
-               break;
-       case 4096:
-               offchip_granularity = V_03093C_X_4K_DWORDS;
-               break;
-       }
-
        assert(!sctx->tf_ring);
+
        /* Use 64K alignment for both rings, so that we can pass the address
         * to shaders as one SGPR containing bits [16:47].
         */
        sctx->tf_ring = si_aligned_buffer_create(sctx->b.b.screen,
-                                                  R600_RESOURCE_FLAG_UNMAPPABLE,
-                                                  PIPE_USAGE_DEFAULT,
-                                                  32768 * sctx->screen->info.max_se,
-                                                  64 * 1024);
+                                                R600_RESOURCE_FLAG_UNMAPPABLE,
+                                                PIPE_USAGE_DEFAULT,
+                                                sctx->screen->tess_factor_ring_size,
+                                                64 * 1024);
        if (!sctx->tf_ring)
                return;
 
-       assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
-
        sctx->tess_offchip_ring =
                si_aligned_buffer_create(sctx->b.b.screen,
-                                          R600_RESOURCE_FLAG_UNMAPPABLE,
-                                          PIPE_USAGE_DEFAULT,
-                                          max_offchip_buffers *
-                                          sctx->screen->tess_offchip_block_dw_size * 4,
-                                          64 * 1024);
+                                        R600_RESOURCE_FLAG_UNMAPPABLE,
+                                        PIPE_USAGE_DEFAULT,
+                                        sctx->screen->tess_offchip_ring_size,
+                                        64 * 1024);
        if (!sctx->tess_offchip_ring)
                return;
 
@@ -3031,27 +3006,22 @@ static void si_init_tess_factor_ring(struct si_context *sctx)
 
        /* Append these registers to the init config state. */
        if (sctx->b.chip_class >= CIK) {
-               if (sctx->b.chip_class >= VI)
-                       --max_offchip_buffers;
-
                si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
-                              S_030938_SIZE(sctx->tf_ring->width0 / 4));
+                              S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
                si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
                               factor_va >> 8);
                if (sctx->b.chip_class >= GFX9)
                        si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
                                       factor_va >> 40);
                si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
-                            S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
-                            S_03093C_OFFCHIP_GRANULARITY(offchip_granularity));
+                              sctx->screen->vgt_hs_offchip_param);
        } else {
-               assert(offchip_granularity == V_03093C_X_8K_DWORDS);
                si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
-                              S_008988_SIZE(sctx->tf_ring->width0 / 4));
+                              S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
                si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
                               factor_va >> 8);
                si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
-                              S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers));
+                              sctx->screen->vgt_hs_offchip_param);
        }
 
        if (sctx->b.chip_class >= GFX9) {