projects / mesa.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | inline | side by side
radeonsi: remove r600_ring::flush callback
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 3643ba500b60b82f02e5d8723f12201e79f945a6..1d3da36215a8f4213ca1e824ddb0f6d477858e02 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -492,7 +492,7 @@ static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
        vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
 
        si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
-       si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
+       si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
 
        shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
                           S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
@@ -518,7 +518,7 @@ static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
 
        if (sscreen->info.chip_class >= GFX9) {
                si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
-               si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, va >> 40);
+               si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
 
                /* We need at least 2 components for LS.
                 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
@@ -535,7 +535,7 @@ static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
                        S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
        } else {
                si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
-               si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
+               si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
 
                shader->config.rsrc2 =
                        S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
@@ -588,7 +588,7 @@ static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
        si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
                       shader->selector->esgs_itemsize / 4);
        si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
-       si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
+       si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
        si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
                       S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
                       S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
@@ -785,14 +785,14 @@ static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
 
                unsigned num_user_sgprs;
                if (es_type == PIPE_SHADER_VERTEX)
-                       num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_GS_NUM_USER_SGPR);
+                       num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
                else
-                       num_user_sgprs = GFX9_GS_NUM_USER_SGPR;
+                       num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
 
                gfx9_get_gs_info(shader->key.part.gs.es, sel, &gs_info);
 
                si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
-               si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, va >> 40);
+               si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
 
                si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
                               S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
@@ -824,7 +824,7 @@ static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
                                             NULL, pm4);
        } else {
                si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
-               si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
+               si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
 
                si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
                               S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
@@ -935,7 +935,7 @@ static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
        oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
 
        si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
-       si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
+       si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
        si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
                       S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
                       S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
@@ -1115,7 +1115,7 @@ static void si_shader_ps(struct si_shader *shader)
        va = shader->bo->gpu_address;
        si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
        si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
-       si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
+       si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
 
        si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
                       S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
@@ -1215,11 +1215,7 @@ static void si_shader_selector_key_hw_vs(struct si_context *sctx,
                                      ps->info.writes_samplemask ||
                                      alpha_to_coverage ||
                                      si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
-
-               unsigned ps_colormask = sctx->framebuffer.colorbuf_enabled_4bit &
-                                       sctx->queued.named.blend->cb_target_mask;
-               if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
-                       ps_colormask &= ps->colors_written_4bit;
+               unsigned ps_colormask = si_get_total_colormask(sctx);
 
                ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
                              (!ps_colormask &&
@@ -1317,6 +1313,7 @@ static inline void si_shader_selector_key(struct pipe_context *ctx,
                                si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
                                                          key, &key->part.gs.vs_prolog);
                                key->part.gs.es = sctx->vs_shader.cso;
+                               key->part.gs.prolog.gfx9_prev_is_vs = 1;
                        }
 
                        /* Merged ES-GS can have unbalanced wave usage.
@@ -1459,6 +1456,23 @@ static inline void si_shader_selector_key(struct pipe_context *ctx,
                }
 
                key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
+
+               /* ps_uses_fbfetch is true only if the color buffer is bound. */
+               if (sctx->ps_uses_fbfetch) {
+                       struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
+                       struct pipe_resource *tex = cb0->texture;
+
+                       /* 1D textures are allocated and used as 2D on GFX9. */
+                       key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
+                       key->mono.u.ps.fbfetch_is_1D = sctx->b.chip_class != GFX9 &&
+                                                      (tex->target == PIPE_TEXTURE_1D ||
+                                                       tex->target == PIPE_TEXTURE_1D_ARRAY);
+                       key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
+                                                        tex->target == PIPE_TEXTURE_2D_ARRAY ||
+                                                        tex->target == PIPE_TEXTURE_CUBE ||
+                                                        tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
+                                                        tex->target == PIPE_TEXTURE_3D;
+               }
                break;
        }
        default:
@@ -2425,6 +2439,7 @@ static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
                        si_mark_atom_dirty(sctx, &sctx->msaa_config);
        }
        si_set_active_descriptors_for_shader(sctx, sel);
+       si_update_ps_colorbuf0_slot(sctx);
 }
 
 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
@@ -2760,7 +2775,7 @@ static bool si_update_gs_ring_buffers(struct si_context *sctx)
 
        /* Flush the context to re-emit both init_config states. */
        sctx->b.initial_gfx_cs_size = 0; /* force flush */
-       si_context_gfx_flush(sctx, PIPE_FLUSH_ASYNC, NULL);
+       si_flush_gfx_cs(sctx, PIPE_FLUSH_ASYNC, NULL);
 
        /* Set ring bindings. */
        if (sctx->esgs_ring) {
@@ -3020,7 +3035,7 @@ static void si_init_tess_factor_ring(struct si_context *sctx)
                               factor_va >> 8);
                if (sctx->b.chip_class >= GFX9)
                        si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
-                                      factor_va >> 40);
+                                      S_030944_BASE_HI(factor_va >> 40));
                si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
                               sctx->screen->vgt_hs_offchip_param);
        } else {
@@ -3037,7 +3052,7 @@ static void si_init_tess_factor_ring(struct si_context *sctx)
         */
        si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
        sctx->b.initial_gfx_cs_size = 0; /* force flush */
-       si_context_gfx_flush(sctx, PIPE_FLUSH_ASYNC, NULL);
+       si_flush_gfx_cs(sctx, PIPE_FLUSH_ASYNC, NULL);
 }
 
 /**