#include "gfx9d.h"
#include "radeon/r600_cs.h"
+#include "compiler/nir/nir_serialize.h"
#include "tgsi/tgsi_parse.h"
#include "tgsi/tgsi_ureg.h"
#include "util/hash_table.h"
/* SHADER_CACHE */
/**
- * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
- * integer.
+ * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
+ * size as integer.
*/
-static void *si_get_tgsi_binary(struct si_shader_selector *sel)
+static void *si_get_ir_binary(struct si_shader_selector *sel)
{
- unsigned tgsi_size = tgsi_num_tokens(sel->tokens) *
- sizeof(struct tgsi_token);
- unsigned size = 4 + tgsi_size + sizeof(sel->so);
- char *result = (char*)MALLOC(size);
+ struct blob blob;
+ unsigned ir_size;
+ void *ir_binary;
+
+ if (sel->tokens) {
+ ir_binary = sel->tokens;
+ ir_size = tgsi_num_tokens(sel->tokens) *
+ sizeof(struct tgsi_token);
+ } else {
+ assert(sel->nir);
+ blob_init(&blob);
+ nir_serialize(&blob, sel->nir);
+ ir_binary = blob.data;
+ ir_size = blob.size;
+ }
+
+ unsigned size = 4 + ir_size + sizeof(sel->so);
+ char *result = (char*)MALLOC(size);
if (!result)
return NULL;
*((uint32_t*)result) = size;
- memcpy(result + 4, sel->tokens, tgsi_size);
- memcpy(result + 4 + tgsi_size, &sel->so, sizeof(sel->so));
+ memcpy(result + 4, ir_binary, ir_size);
+ memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so));
+
+ if (sel->nir)
+ blob_finish(&blob);
+
return result;
}
* Insert a shader into the cache. It's assumed the shader is not in the cache.
* Use si_shader_cache_load_shader before calling this.
*
- * Returns false on failure, in which case the tgsi_binary should be freed.
+ * Returns false on failure, in which case the ir_binary should be freed.
*/
static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
- void *tgsi_binary,
+ void *ir_binary,
struct si_shader *shader,
bool insert_into_disk_cache)
{
struct hash_entry *entry;
uint8_t key[CACHE_KEY_SIZE];
- entry = _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
+ entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
if (entry)
return false; /* already added */
if (!hw_binary)
return false;
- if (_mesa_hash_table_insert(sscreen->shader_cache, tgsi_binary,
+ if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
hw_binary) == NULL) {
FREE(hw_binary);
return false;
}
if (sscreen->disk_shader_cache && insert_into_disk_cache) {
- disk_cache_compute_key(sscreen->disk_shader_cache, tgsi_binary,
- *((uint32_t *)tgsi_binary), key);
+ disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
+ *((uint32_t *)ir_binary), key);
disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
*((uint32_t *) hw_binary), NULL);
}
}
static bool si_shader_cache_load_shader(struct si_screen *sscreen,
- void *tgsi_binary,
+ void *ir_binary,
struct si_shader *shader)
{
struct hash_entry *entry =
- _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
+ _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
if (!entry) {
if (sscreen->disk_shader_cache) {
unsigned char sha1[CACHE_KEY_SIZE];
- size_t tg_size = *((uint32_t *) tgsi_binary);
+ size_t tg_size = *((uint32_t *) ir_binary);
disk_cache_compute_key(sscreen->disk_shader_cache,
- tgsi_binary, tg_size, sha1);
+ ir_binary, tg_size, sha1);
size_t binary_size;
uint8_t *buffer =
}
free(buffer);
- if (!si_shader_cache_insert_shader(sscreen, tgsi_binary,
+ if (!si_shader_cache_insert_shader(sscreen, ir_binary,
shader, false))
- FREE(tgsi_binary);
+ FREE(ir_binary);
} else {
return false;
}
} else {
if (si_load_shader_binary(shader, entry->data))
- FREE(tgsi_binary);
+ FREE(ir_binary);
else
return false;
}
return shader->pm4;
}
+static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
+{
+ /* Add the pointer to VBO descriptors. */
+ if (HAVE_32BIT_POINTERS) {
+ return num_always_on_user_sgprs + 1;
+ } else {
+ assert(num_always_on_user_sgprs % 2 == 0);
+ return num_always_on_user_sgprs + 2;
+ }
+}
+
static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
{
struct si_pm4_state *pm4;
vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
- si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
+ si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
S_00B528_DX10_CLAMP(1) |
S_00B528_FLOAT_MODE(shader->config.float_mode);
- shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_VS_NUM_USER_SGPR) |
+ shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
}
if (sscreen->info.chip_class >= GFX9) {
si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
- si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, va >> 40);
+ si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
/* We need at least 2 components for LS.
* VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
*/
ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
+ unsigned num_user_sgprs =
+ si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
+
shader->config.rsrc2 =
- S_00B42C_USER_SGPR(GFX9_TCS_NUM_USER_SGPR) |
- S_00B42C_USER_SGPR_MSB(GFX9_TCS_NUM_USER_SGPR >> 5) |
+ S_00B42C_USER_SGPR(num_user_sgprs) |
+ S_00B42C_USER_SGPR_MSB(num_user_sgprs >> 5) |
S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
} else {
si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
- si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
+ si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
shader->config.rsrc2 =
S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
if (shader->selector->type == PIPE_SHADER_VERTEX) {
/* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
- num_user_sgprs = SI_VS_NUM_USER_SGPR;
+ num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
} else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
num_user_sgprs = SI_TES_NUM_USER_SGPR;
si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
shader->selector->esgs_itemsize / 4);
si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
- si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
+ si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
else
gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
+ unsigned num_user_sgprs;
+ if (es_type == PIPE_SHADER_VERTEX)
+ num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
+ else
+ num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
+
gfx9_get_gs_info(shader->key.part.gs.es, sel, &gs_info);
si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
- si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, va >> 40);
+ si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
S_00B228_FLOAT_MODE(shader->config.float_mode) |
S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
- S_00B22C_USER_SGPR(GFX9_GS_NUM_USER_SGPR) |
- S_00B22C_USER_SGPR_MSB(GFX9_GS_NUM_USER_SGPR >> 5) |
+ S_00B22C_USER_SGPR(num_user_sgprs) |
+ S_00B22C_USER_SGPR_MSB(num_user_sgprs >> 5) |
S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
S_00B22C_LDS_SIZE(gs_info.lds_size) |
NULL, pm4);
} else {
si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
- si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
+ si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
} else {
- num_user_sgprs = SI_VS_NUM_USER_SGPR;
+ num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
}
} else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
vgpr_comp_cnt = enable_prim_id ? 3 : 2;
oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
- si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
+ si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
va = shader->bo->gpu_address;
si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
- si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
+ si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
/* Find out if PS is disabled. */
bool ps_disabled = true;
if (ps) {
+ const struct si_state_blend *blend = sctx->queued.named.blend;
+ bool alpha_to_coverage = blend && blend->alpha_to_coverage;
bool ps_modifies_zs = ps->info.uses_kill ||
ps->info.writes_z ||
ps->info.writes_stencil ||
ps->info.writes_samplemask ||
+ alpha_to_coverage ||
si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
-
- unsigned ps_colormask = sctx->framebuffer.colorbuf_enabled_4bit &
- sctx->queued.named.blend->cb_target_mask;
- if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
- ps_colormask &= ps->colors_written_4bit;
+ unsigned ps_colormask = si_get_total_colormask(sctx);
ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
(!ps_colormask &&
si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
key, &key->part.gs.vs_prolog);
key->part.gs.es = sctx->vs_shader.cso;
+ key->part.gs.prolog.gfx9_prev_is_vs = 1;
}
/* Merged ES-GS can have unbalanced wave usage.
}
key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
+
+ /* ps_uses_fbfetch is true only if the color buffer is bound. */
+ if (sctx->ps_uses_fbfetch) {
+ struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
+ struct pipe_resource *tex = cb0->texture;
+
+ /* 1D textures are allocated and used as 2D on GFX9. */
+ key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
+ key->mono.u.ps.fbfetch_is_1D = sctx->b.chip_class != GFX9 &&
+ (tex->target == PIPE_TEXTURE_1D ||
+ tex->target == PIPE_TEXTURE_1D_ARRAY);
+ key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
+ tex->target == PIPE_TEXTURE_2D_ARRAY ||
+ tex->target == PIPE_TEXTURE_CUBE ||
+ tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
+ tex->target == PIPE_TEXTURE_3D;
+ }
break;
}
default:
struct si_screen *sscreen = sel->screen;
LLVMTargetMachineRef tm;
struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
- unsigned i;
assert(!debug->debug_message || debug->async);
assert(thread_index >= 0);
*/
if (!sscreen->use_monolithic_shaders) {
struct si_shader *shader = CALLOC_STRUCT(si_shader);
- void *tgsi_binary = NULL;
+ void *ir_binary = NULL;
if (!shader) {
fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
sel->so.num_outputs != 0,
&shader->key);
- if (sel->tokens)
- tgsi_binary = si_get_tgsi_binary(sel);
+ if (sel->tokens || sel->nir)
+ ir_binary = si_get_ir_binary(sel);
/* Try to load the shader from the shader cache. */
mtx_lock(&sscreen->shader_cache_mutex);
- if (tgsi_binary &&
- si_shader_cache_load_shader(sscreen, tgsi_binary, shader)) {
+ if (ir_binary &&
+ si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
mtx_unlock(&sscreen->shader_cache_mutex);
+ si_shader_dump_stats_for_shader_db(shader, debug);
} else {
mtx_unlock(&sscreen->shader_cache_mutex);
if (si_compile_tgsi_shader(sscreen, tm, shader, false,
debug) != 0) {
FREE(shader);
- FREE(tgsi_binary);
+ FREE(ir_binary);
fprintf(stderr, "radeonsi: can't compile a main shader part\n");
return;
}
- if (tgsi_binary) {
+ if (ir_binary) {
mtx_lock(&sscreen->shader_cache_mutex);
- if (!si_shader_cache_insert_shader(sscreen, tgsi_binary, shader, true))
- FREE(tgsi_binary);
+ if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
+ FREE(ir_binary);
mtx_unlock(&sscreen->shader_cache_mutex);
}
}
}
}
- /* Pre-compilation. */
- if (sscreen->debug_flags & DBG(PRECOMPILE) &&
- /* GFX9 needs LS or ES for compilation, which we don't have here. */
- (sscreen->info.chip_class <= VI ||
- (sel->type != PIPE_SHADER_TESS_CTRL &&
- sel->type != PIPE_SHADER_GEOMETRY))) {
- struct si_shader_ctx_state state = {sel};
- struct si_shader_key key;
-
- memset(&key, 0, sizeof(key));
- si_parse_next_shader_property(&sel->info,
- sel->so.num_outputs != 0,
- &key);
-
- /* GFX9 doesn't have LS and ES. */
- if (sscreen->info.chip_class >= GFX9) {
- key.as_ls = 0;
- key.as_es = 0;
- }
-
- /* Set reasonable defaults, so that the shader key doesn't
- * cause any code to be eliminated.
- */
- switch (sel->type) {
- case PIPE_SHADER_TESS_CTRL:
- key.part.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
- break;
- case PIPE_SHADER_FRAGMENT:
- key.part.ps.prolog.bc_optimize_for_persp =
- sel->info.uses_persp_center &&
- sel->info.uses_persp_centroid;
- key.part.ps.prolog.bc_optimize_for_linear =
- sel->info.uses_linear_center &&
- sel->info.uses_linear_centroid;
- key.part.ps.epilog.alpha_func = PIPE_FUNC_ALWAYS;
- for (i = 0; i < 8; i++)
- if (sel->info.colors_written & (1 << i))
- key.part.ps.epilog.spi_shader_col_format |=
- V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
- break;
- }
-
- if (si_shader_select_with_key(sscreen, &state,
- &sel->compiler_ctx_state, &key,
- thread_index))
- fprintf(stderr, "radeonsi: can't create a monolithic shader\n");
- }
-
/* The GS copy shader is always pre-compiled. */
if (sel->type == PIPE_SHADER_GEOMETRY) {
sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, tm, sel, debug);
sel->nir = state->ir.nir;
si_nir_scan_shader(sel->nir, &sel->info);
+ si_nir_scan_tess_ctrl(sel->nir, &sel->info, &sel->tcs_info);
si_lower_nir(sel);
}
si_mark_atom_dirty(sctx, &sctx->msaa_config);
}
si_set_active_descriptors_for_shader(sctx, sel);
+ si_update_ps_colorbuf0_slot(sctx);
}
static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
/* Flush the context to re-emit both init_config states. */
sctx->b.initial_gfx_cs_size = 0; /* force flush */
- si_context_gfx_flush(sctx, PIPE_FLUSH_ASYNC, NULL);
+ si_flush_gfx_cs(sctx, PIPE_FLUSH_ASYNC, NULL);
/* Set ring bindings. */
if (sctx->esgs_ring) {
static void si_init_tess_factor_ring(struct si_context *sctx)
{
- bool double_offchip_buffers = sctx->b.chip_class >= CIK &&
- sctx->b.family != CHIP_CARRIZO &&
- sctx->b.family != CHIP_STONEY;
- /* This must be one less than the maximum number due to a hw limitation.
- * Various hardware bugs in SI, CIK, and GFX9 need this.
- */
- unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
- unsigned max_offchip_buffers = max_offchip_buffers_per_se *
- sctx->screen->info.max_se;
- unsigned offchip_granularity;
-
- switch (sctx->screen->tess_offchip_block_dw_size) {
- default:
- assert(0);
- /* fall through */
- case 8192:
- offchip_granularity = V_03093C_X_8K_DWORDS;
- break;
- case 4096:
- offchip_granularity = V_03093C_X_4K_DWORDS;
- break;
- }
+ assert(!sctx->tess_rings);
- assert(!sctx->tf_ring);
- /* Use 64K alignment for both rings, so that we can pass the address
- * to shaders as one SGPR containing bits [16:47].
+ /* The address must be aligned to 2^19, because the shader only
+ * receives the high 13 bits.
*/
- sctx->tf_ring = si_aligned_buffer_create(sctx->b.b.screen,
- R600_RESOURCE_FLAG_UNMAPPABLE,
- PIPE_USAGE_DEFAULT,
- 32768 * sctx->screen->info.max_se,
- 64 * 1024);
- if (!sctx->tf_ring)
- return;
-
- assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
-
- sctx->tess_offchip_ring =
- si_aligned_buffer_create(sctx->b.b.screen,
- R600_RESOURCE_FLAG_UNMAPPABLE,
- PIPE_USAGE_DEFAULT,
- max_offchip_buffers *
- sctx->screen->tess_offchip_block_dw_size * 4,
- 64 * 1024);
- if (!sctx->tess_offchip_ring)
+ sctx->tess_rings = si_aligned_buffer_create(sctx->b.b.screen,
+ R600_RESOURCE_FLAG_32BIT,
+ PIPE_USAGE_DEFAULT,
+ sctx->screen->tess_offchip_ring_size +
+ sctx->screen->tess_factor_ring_size,
+ 1 << 19);
+ if (!sctx->tess_rings)
return;
si_init_config_add_vgt_flush(sctx);
- uint64_t offchip_va = r600_resource(sctx->tess_offchip_ring)->gpu_address;
- uint64_t factor_va = r600_resource(sctx->tf_ring)->gpu_address;
- assert((offchip_va & 0xffff) == 0);
- assert((factor_va & 0xffff) == 0);
-
- si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tess_offchip_ring),
- RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
- si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tf_ring),
+ si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tess_rings),
RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
+ uint64_t factor_va = r600_resource(sctx->tess_rings)->gpu_address +
+ sctx->screen->tess_offchip_ring_size;
+
/* Append these registers to the init config state. */
if (sctx->b.chip_class >= CIK) {
- if (sctx->b.chip_class >= VI)
- --max_offchip_buffers;
-
si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
- S_030938_SIZE(sctx->tf_ring->width0 / 4));
+ S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
factor_va >> 8);
if (sctx->b.chip_class >= GFX9)
si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
- factor_va >> 40);
+ S_030944_BASE_HI(factor_va >> 40));
si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
- S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
- S_03093C_OFFCHIP_GRANULARITY(offchip_granularity));
+ sctx->screen->vgt_hs_offchip_param);
} else {
- assert(offchip_granularity == V_03093C_X_8K_DWORDS);
si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
- S_008988_SIZE(sctx->tf_ring->width0 / 4));
+ S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
factor_va >> 8);
si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
- S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers));
- }
-
- if (sctx->b.chip_class >= GFX9) {
- si_pm4_set_reg(sctx->init_config,
- R_00B430_SPI_SHADER_USER_DATA_LS_0 +
- GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K * 4,
- offchip_va >> 16);
- si_pm4_set_reg(sctx->init_config,
- R_00B430_SPI_SHADER_USER_DATA_LS_0 +
- GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K * 4,
- factor_va >> 16);
- } else {
- si_pm4_set_reg(sctx->init_config,
- R_00B430_SPI_SHADER_USER_DATA_HS_0 +
- GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K * 4,
- offchip_va >> 16);
- si_pm4_set_reg(sctx->init_config,
- R_00B430_SPI_SHADER_USER_DATA_HS_0 +
- GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K * 4,
- factor_va >> 16);
+ sctx->screen->vgt_hs_offchip_param);
}
/* Flush the context to re-emit the init_config state.
*/
si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
sctx->b.initial_gfx_cs_size = 0; /* force flush */
- si_context_gfx_flush(sctx, PIPE_FLUSH_ASYNC, NULL);
+ si_flush_gfx_cs(sctx, PIPE_FLUSH_ASYNC, NULL);
}
/**
/* Update stages before GS. */
if (sctx->tes_shader.cso) {
- if (!sctx->tf_ring) {
+ if (!sctx->tess_rings) {
si_init_tess_factor_ring(sctx);
- if (!sctx->tf_ring)
+ if (!sctx->tess_rings)
return false;
}