/*
* Copyright 2012 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "si_pipe.h"
-#include "sid.h"
+#include "si_build_pm4.h"
#include "gfx9d.h"
-#include "radeon/r600_cs.h"
+#include "compiler/nir/nir_serialize.h"
#include "tgsi/tgsi_parse.h"
#include "tgsi/tgsi_ureg.h"
#include "util/hash_table.h"
#include "util/disk_cache.h"
#include "util/mesa-sha1.h"
#include "ac_exp_param.h"
+#include "ac_shader_util.h"
/* SHADER_CACHE */
/**
- * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
- * integer.
+ * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
+ * size as integer.
*/
-static void *si_get_tgsi_binary(struct si_shader_selector *sel)
+void *si_get_ir_binary(struct si_shader_selector *sel)
{
- unsigned tgsi_size = tgsi_num_tokens(sel->tokens) *
- sizeof(struct tgsi_token);
- unsigned size = 4 + tgsi_size + sizeof(sel->so);
- char *result = (char*)MALLOC(size);
+ struct blob blob;
+ unsigned ir_size;
+ void *ir_binary;
+
+ if (sel->tokens) {
+ ir_binary = sel->tokens;
+ ir_size = tgsi_num_tokens(sel->tokens) *
+ sizeof(struct tgsi_token);
+ } else {
+ assert(sel->nir);
+
+ blob_init(&blob);
+ nir_serialize(&blob, sel->nir);
+ ir_binary = blob.data;
+ ir_size = blob.size;
+ }
+ unsigned size = 4 + ir_size + sizeof(sel->so);
+ char *result = (char*)MALLOC(size);
if (!result)
return NULL;
*((uint32_t*)result) = size;
- memcpy(result + 4, sel->tokens, tgsi_size);
- memcpy(result + 4 + tgsi_size, &sel->so, sizeof(sel->so));
+ memcpy(result + 4, ir_binary, ir_size);
+ memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so));
+
+ if (sel->nir)
+ blob_finish(&blob);
+
return result;
}
* Insert a shader into the cache. It's assumed the shader is not in the cache.
* Use si_shader_cache_load_shader before calling this.
*
- * Returns false on failure, in which case the tgsi_binary should be freed.
+ * Returns false on failure, in which case the ir_binary should be freed.
*/
-static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
- void *tgsi_binary,
- struct si_shader *shader,
- bool insert_into_disk_cache)
+bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
+ struct si_shader *shader,
+ bool insert_into_disk_cache)
{
void *hw_binary;
struct hash_entry *entry;
uint8_t key[CACHE_KEY_SIZE];
- entry = _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
+ entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
if (entry)
return false; /* already added */
if (!hw_binary)
return false;
- if (_mesa_hash_table_insert(sscreen->shader_cache, tgsi_binary,
+ if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
hw_binary) == NULL) {
FREE(hw_binary);
return false;
}
if (sscreen->disk_shader_cache && insert_into_disk_cache) {
- disk_cache_compute_key(sscreen->disk_shader_cache, tgsi_binary,
- *((uint32_t *)tgsi_binary), key);
+ disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
+ *((uint32_t *)ir_binary), key);
disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
*((uint32_t *) hw_binary), NULL);
}
return true;
}
-static bool si_shader_cache_load_shader(struct si_screen *sscreen,
- void *tgsi_binary,
- struct si_shader *shader)
+bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
+ struct si_shader *shader)
{
struct hash_entry *entry =
- _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
+ _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
if (!entry) {
if (sscreen->disk_shader_cache) {
unsigned char sha1[CACHE_KEY_SIZE];
- size_t tg_size = *((uint32_t *) tgsi_binary);
+ size_t tg_size = *((uint32_t *) ir_binary);
disk_cache_compute_key(sscreen->disk_shader_cache,
- tgsi_binary, tg_size, sha1);
+ ir_binary, tg_size, sha1);
size_t binary_size;
uint8_t *buffer =
}
free(buffer);
- if (!si_shader_cache_insert_shader(sscreen, tgsi_binary,
+ if (!si_shader_cache_insert_shader(sscreen, ir_binary,
shader, false))
- FREE(tgsi_binary);
+ FREE(ir_binary);
} else {
return false;
}
} else {
if (si_load_shader_binary(shader, entry->data))
- FREE(tgsi_binary);
+ FREE(ir_binary);
else
return false;
}
return shader->pm4;
}
+static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
+{
+ /* Add the pointer to VBO descriptors. */
+ if (HAVE_32BIT_POINTERS) {
+ return num_always_on_user_sgprs + 1;
+ } else {
+ assert(num_always_on_user_sgprs % 2 == 0);
+ return num_always_on_user_sgprs + 2;
+ }
+}
+
static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
{
struct si_pm4_state *pm4;
vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
- si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
+ si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
S_00B528_DX10_CLAMP(1) |
S_00B528_FLOAT_MODE(shader->config.float_mode);
- shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_VS_NUM_USER_SGPR) |
+ shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
}
if (sscreen->info.chip_class >= GFX9) {
si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
- si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, va >> 40);
+ si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
/* We need at least 2 components for LS.
* VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
*/
ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
+ unsigned num_user_sgprs =
+ si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
+
shader->config.rsrc2 =
- S_00B42C_USER_SGPR(GFX9_TCS_NUM_USER_SGPR) |
- S_00B42C_USER_SGPR_MSB(GFX9_TCS_NUM_USER_SGPR >> 5) |
+ S_00B42C_USER_SGPR(num_user_sgprs) |
+ S_00B42C_USER_SGPR_MSB(num_user_sgprs >> 5) |
S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
} else {
si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
- si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
+ si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
shader->config.rsrc2 =
S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
if (shader->selector->type == PIPE_SHADER_VERTEX) {
/* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
- num_user_sgprs = SI_VS_NUM_USER_SGPR;
+ num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
} else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
num_user_sgprs = SI_TES_NUM_USER_SGPR;
si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
shader->selector->esgs_itemsize / 4);
si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
- si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
+ si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
}
-/**
- * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
- * geometry shader.
- */
-static uint32_t si_vgt_gs_mode(struct si_shader_selector *sel)
-{
- enum chip_class chip_class = sel->screen->info.chip_class;
- unsigned gs_max_vert_out = sel->gs_max_out_vertices;
- unsigned cut_mode;
-
- if (gs_max_vert_out <= 128) {
- cut_mode = V_028A40_GS_CUT_128;
- } else if (gs_max_vert_out <= 256) {
- cut_mode = V_028A40_GS_CUT_256;
- } else if (gs_max_vert_out <= 512) {
- cut_mode = V_028A40_GS_CUT_512;
- } else {
- assert(gs_max_vert_out <= 1024);
- cut_mode = V_028A40_GS_CUT_1024;
- }
+static unsigned si_conv_prim_to_gs_out(unsigned mode)
+{
+ static const int prim_conv[] = {
+ [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
+ [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
+ [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
+ [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
+ [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
+ [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
+ [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
+ };
+ assert(mode < ARRAY_SIZE(prim_conv));
- return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
- S_028A40_CUT_MODE(cut_mode)|
- S_028A40_ES_WRITE_OPTIMIZE(chip_class <= VI) |
- S_028A40_GS_WRITE_OPTIMIZE(1) |
- S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0);
+ return prim_conv[mode];
}
struct gfx9_gs_info {
if (max_stream >= 2)
offset += num_components[2] * sel->gs_max_out_vertices;
si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, offset);
+ si_pm4_set_reg(pm4, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
+ si_conv_prim_to_gs_out(sel->gs_output_prim));
if (max_stream >= 3)
offset += num_components[3] * sel->gs_max_out_vertices;
si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
else
gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
+ unsigned num_user_sgprs;
+ if (es_type == PIPE_SHADER_VERTEX)
+ num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
+ else
+ num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
+
gfx9_get_gs_info(shader->key.part.gs.es, sel, &gs_info);
si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
- si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, va >> 40);
+ si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
S_00B228_FLOAT_MODE(shader->config.float_mode) |
S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
- S_00B22C_USER_SGPR(GFX9_GS_NUM_USER_SGPR) |
- S_00B22C_USER_SGPR_MSB(GFX9_GS_NUM_USER_SGPR >> 5) |
+ S_00B22C_USER_SGPR(num_user_sgprs) |
+ S_00B22C_USER_SGPR_MSB(num_user_sgprs >> 5) |
S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
S_00B22C_LDS_SIZE(gs_info.lds_size) |
NULL, pm4);
} else {
si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
- si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
+ si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, S_028A40_MODE(mode));
si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
} else {
- si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
+ si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
+ ac_vgt_gs_mode(gs->gs_max_out_vertices,
+ sscreen->info.chip_class));
si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
}
num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
} else {
- num_user_sgprs = SI_VS_NUM_USER_SGPR;
+ num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
}
} else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
vgpr_comp_cnt = enable_prim_id ? 3 : 2;
oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
- si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
+ si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
return value;
}
-static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
-{
- unsigned i, cb_shader_mask = 0;
-
- for (i = 0; i < 8; i++) {
- switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
- case V_028714_SPI_SHADER_ZERO:
- break;
- case V_028714_SPI_SHADER_32_R:
- cb_shader_mask |= 0x1 << (i * 4);
- break;
- case V_028714_SPI_SHADER_32_GR:
- cb_shader_mask |= 0x3 << (i * 4);
- break;
- case V_028714_SPI_SHADER_32_AR:
- cb_shader_mask |= 0x9 << (i * 4);
- break;
- case V_028714_SPI_SHADER_FP16_ABGR:
- case V_028714_SPI_SHADER_UNORM16_ABGR:
- case V_028714_SPI_SHADER_SNORM16_ABGR:
- case V_028714_SPI_SHADER_UINT16_ABGR:
- case V_028714_SPI_SHADER_SINT16_ABGR:
- case V_028714_SPI_SHADER_32_ABGR:
- cb_shader_mask |= 0xf << (i * 4);
- break;
- default:
- assert(0);
- }
- }
- return cb_shader_mask;
-}
-
static void si_shader_ps(struct si_shader *shader)
{
struct tgsi_shader_info *info = &shader->selector->info;
spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
spi_shader_col_format = si_get_spi_shader_col_format(shader);
- cb_shader_mask = si_get_cb_shader_mask(spi_shader_col_format);
+ cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
/* Ensure that some export memory is always allocated, for two reasons:
*
si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
- si_get_spi_shader_z_format(info->writes_z,
+ ac_get_spi_shader_z_format(info->writes_z,
info->writes_stencil,
info->writes_samplemask));
va = shader->bo->gpu_address;
si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
- si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
+ si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
/* Find out if PS is disabled. */
bool ps_disabled = true;
if (ps) {
+ const struct si_state_blend *blend = sctx->queued.named.blend;
+ bool alpha_to_coverage = blend && blend->alpha_to_coverage;
bool ps_modifies_zs = ps->info.uses_kill ||
ps->info.writes_z ||
ps->info.writes_stencil ||
ps->info.writes_samplemask ||
+ alpha_to_coverage ||
si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
-
- unsigned ps_colormask = sctx->framebuffer.colorbuf_enabled_4bit &
- sctx->queued.named.blend->cb_target_mask;
- if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
- ps_colormask &= ps->colors_written_4bit;
+ unsigned ps_colormask = si_get_total_colormask(sctx);
ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
(!ps_colormask &&
}
/* Find out which VS outputs aren't used by the PS. */
- uint64_t outputs_written = vs->outputs_written;
+ uint64_t outputs_written = vs->outputs_written_before_ps;
uint64_t inputs_read = 0;
- /* ignore POSITION, PSIZE */
- outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0) |
- (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0))));
+ /* Ignore outputs that are not passed from VS to PS. */
+ outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
+ (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
+ (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
if (!ps_disabled) {
inputs_read = ps->inputs_read;
}
break;
case PIPE_SHADER_TESS_CTRL:
- if (sctx->b.chip_class >= GFX9) {
+ if (sctx->chip_class >= GFX9) {
si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
key, &key->part.tcs.ls_prolog);
key->part.tcs.ls = sctx->vs_shader.cso;
}
break;
case PIPE_SHADER_GEOMETRY:
- if (sctx->b.chip_class >= GFX9) {
+ if (sctx->chip_class >= GFX9) {
if (sctx->tes_shader.cso) {
key->part.gs.es = sctx->tes_shader.cso;
} else {
si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
key, &key->part.gs.vs_prolog);
key->part.gs.es = sctx->vs_shader.cso;
+ key->part.gs.prolog.gfx9_prev_is_vs = 1;
}
/* Merged ES-GS can have unbalanced wave usage.
* to the range supported by the type if a channel has less
* than 16 bits and the export format is 16_ABGR.
*/
- if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII) {
+ if (sctx->chip_class <= CIK && sctx->family != CHIP_HAWAII) {
key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
}
key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
}
- if (rs) {
- bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
- sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
- sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
- bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
+ bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
+ bool is_line = util_prim_is_lines(sctx->current_rast_prim);
- key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
- key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
+ key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
+ key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
- if (sctx->queued.named.blend) {
- key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
- rs->multisample_enable;
- }
+ if (sctx->queued.named.blend) {
+ key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
+ rs->multisample_enable;
+ }
- key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
- key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
- (is_line && rs->line_smooth)) &&
- sctx->framebuffer.nr_samples <= 1;
- key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
+ key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
+ key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
+ (is_line && rs->line_smooth)) &&
+ sctx->framebuffer.nr_samples <= 1;
+ key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
- if (sctx->ps_iter_samples > 1 &&
- sel->info.reads_samplemask) {
- key->part.ps.prolog.samplemask_log_ps_iter =
- util_logbase2(util_next_power_of_two(sctx->ps_iter_samples));
- }
+ if (sctx->ps_iter_samples > 1 &&
+ sel->info.reads_samplemask) {
+ key->part.ps.prolog.samplemask_log_ps_iter =
+ util_logbase2(sctx->ps_iter_samples);
+ }
- if (rs->force_persample_interp &&
- rs->multisample_enable &&
- sctx->framebuffer.nr_samples > 1 &&
- sctx->ps_iter_samples > 1) {
- key->part.ps.prolog.force_persp_sample_interp =
- sel->info.uses_persp_center ||
- sel->info.uses_persp_centroid;
-
- key->part.ps.prolog.force_linear_sample_interp =
- sel->info.uses_linear_center ||
- sel->info.uses_linear_centroid;
- } else if (rs->multisample_enable &&
- sctx->framebuffer.nr_samples > 1) {
- key->part.ps.prolog.bc_optimize_for_persp =
- sel->info.uses_persp_center &&
- sel->info.uses_persp_centroid;
- key->part.ps.prolog.bc_optimize_for_linear =
- sel->info.uses_linear_center &&
- sel->info.uses_linear_centroid;
- } else {
- /* Make sure SPI doesn't compute more than 1 pair
- * of (i,j), which is the optimization here. */
- key->part.ps.prolog.force_persp_center_interp =
- sel->info.uses_persp_center +
- sel->info.uses_persp_centroid +
- sel->info.uses_persp_sample > 1;
-
- key->part.ps.prolog.force_linear_center_interp =
- sel->info.uses_linear_center +
- sel->info.uses_linear_centroid +
- sel->info.uses_linear_sample > 1;
-
- if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE])
- key->mono.u.ps.interpolate_at_sample_force_center = 1;
- }
+ if (rs->force_persample_interp &&
+ rs->multisample_enable &&
+ sctx->framebuffer.nr_samples > 1 &&
+ sctx->ps_iter_samples > 1) {
+ key->part.ps.prolog.force_persp_sample_interp =
+ sel->info.uses_persp_center ||
+ sel->info.uses_persp_centroid;
+
+ key->part.ps.prolog.force_linear_sample_interp =
+ sel->info.uses_linear_center ||
+ sel->info.uses_linear_centroid;
+ } else if (rs->multisample_enable &&
+ sctx->framebuffer.nr_samples > 1) {
+ key->part.ps.prolog.bc_optimize_for_persp =
+ sel->info.uses_persp_center &&
+ sel->info.uses_persp_centroid;
+ key->part.ps.prolog.bc_optimize_for_linear =
+ sel->info.uses_linear_center &&
+ sel->info.uses_linear_centroid;
+ } else {
+ /* Make sure SPI doesn't compute more than 1 pair
+ * of (i,j), which is the optimization here. */
+ key->part.ps.prolog.force_persp_center_interp =
+ sel->info.uses_persp_center +
+ sel->info.uses_persp_centroid +
+ sel->info.uses_persp_sample > 1;
+
+ key->part.ps.prolog.force_linear_center_interp =
+ sel->info.uses_linear_center +
+ sel->info.uses_linear_centroid +
+ sel->info.uses_linear_sample > 1;
+
+ if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE])
+ key->mono.u.ps.interpolate_at_sample_force_center = 1;
}
key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
+
+ /* ps_uses_fbfetch is true only if the color buffer is bound. */
+ if (sctx->ps_uses_fbfetch) {
+ struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
+ struct pipe_resource *tex = cb0->texture;
+
+ /* 1D textures are allocated and used as 2D on GFX9. */
+ key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
+ key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
+ (tex->target == PIPE_TEXTURE_1D ||
+ tex->target == PIPE_TEXTURE_1D_ARRAY);
+ key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
+ tex->target == PIPE_TEXTURE_2D_ARRAY ||
+ tex->target == PIPE_TEXTURE_CUBE ||
+ tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
+ tex->target == PIPE_TEXTURE_3D;
+ }
break;
}
default:
{
struct si_shader_selector *sel = shader->selector;
struct si_screen *sscreen = sel->screen;
- LLVMTargetMachineRef tm;
+ struct ac_llvm_compiler *compiler;
struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
int r;
if (thread_index >= 0) {
if (low_priority) {
- assert(thread_index < ARRAY_SIZE(sscreen->tm_low_priority));
- tm = sscreen->tm_low_priority[thread_index];
+ assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
+ compiler = &sscreen->compiler_lowp[thread_index];
} else {
- assert(thread_index < ARRAY_SIZE(sscreen->tm));
- tm = sscreen->tm[thread_index];
+ assert(thread_index < ARRAY_SIZE(sscreen->compiler));
+ compiler = &sscreen->compiler[thread_index];
}
if (!debug->async)
debug = NULL;
} else {
assert(!low_priority);
- tm = shader->compiler_ctx_state.tm;
+ compiler = shader->compiler_ctx_state.compiler;
}
- r = si_shader_create(sscreen, tm, shader, debug);
+ r = si_shader_create(sscreen, compiler, shader, debug);
if (unlikely(r)) {
- R600_ERR("Failed to build shader variant (type=%u) %d\n",
+ PRINT_ERR("Failed to build shader variant (type=%u) %d\n",
sel->type, r);
shader->compilation_failed = true;
return;
main_part->selector = sel;
main_part->key.as_es = key->as_es;
main_part->key.as_ls = key->as_ls;
+ main_part->is_monolithic = false;
- if (si_compile_tgsi_shader(sscreen, compiler_state->tm,
- main_part, false,
- &compiler_state->debug) != 0) {
+ if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
+ main_part, &compiler_state->debug) != 0) {
FREE(main_part);
return false;
}
{
struct si_shader_selector *sel = (struct si_shader_selector *)job;
struct si_screen *sscreen = sel->screen;
- LLVMTargetMachineRef tm;
+ struct ac_llvm_compiler *compiler;
struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
- unsigned i;
assert(!debug->debug_message || debug->async);
assert(thread_index >= 0);
- assert(thread_index < ARRAY_SIZE(sscreen->tm));
- tm = sscreen->tm[thread_index];
+ assert(thread_index < ARRAY_SIZE(sscreen->compiler));
+ compiler = &sscreen->compiler[thread_index];
/* Compile the main shader part for use with a prolog and/or epilog.
* If this fails, the driver will try to compile a monolithic shader
*/
if (!sscreen->use_monolithic_shaders) {
struct si_shader *shader = CALLOC_STRUCT(si_shader);
- void *tgsi_binary = NULL;
+ void *ir_binary = NULL;
if (!shader) {
fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
util_queue_fence_init(&shader->ready);
shader->selector = sel;
+ shader->is_monolithic = false;
si_parse_next_shader_property(&sel->info,
sel->so.num_outputs != 0,
&shader->key);
- if (sel->tokens)
- tgsi_binary = si_get_tgsi_binary(sel);
+ if (sel->tokens || sel->nir)
+ ir_binary = si_get_ir_binary(sel);
/* Try to load the shader from the shader cache. */
mtx_lock(&sscreen->shader_cache_mutex);
- if (tgsi_binary &&
- si_shader_cache_load_shader(sscreen, tgsi_binary, shader)) {
+ if (ir_binary &&
+ si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
mtx_unlock(&sscreen->shader_cache_mutex);
+ si_shader_dump_stats_for_shader_db(shader, debug);
} else {
mtx_unlock(&sscreen->shader_cache_mutex);
/* Compile the shader if it hasn't been loaded from the cache. */
- if (si_compile_tgsi_shader(sscreen, tm, shader, false,
+ if (si_compile_tgsi_shader(sscreen, compiler, shader,
debug) != 0) {
FREE(shader);
- FREE(tgsi_binary);
+ FREE(ir_binary);
fprintf(stderr, "radeonsi: can't compile a main shader part\n");
return;
}
- if (tgsi_binary) {
+ if (ir_binary) {
mtx_lock(&sscreen->shader_cache_mutex);
- if (!si_shader_cache_insert_shader(sscreen, tgsi_binary, shader, true))
- FREE(tgsi_binary);
+ if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
+ FREE(ir_binary);
mtx_unlock(&sscreen->shader_cache_mutex);
}
}
break;
/* fall through */
default:
- id = si_shader_io_get_unique_index(name, index);
- sel->outputs_written &= ~(1ull << id);
+ id = si_shader_io_get_unique_index(name, index, true);
+ sel->outputs_written_before_ps &= ~(1ull << id);
break;
case TGSI_SEMANTIC_POSITION: /* ignore these */
case TGSI_SEMANTIC_PSIZE:
}
}
- /* Pre-compilation. */
- if (sscreen->debug_flags & DBG(PRECOMPILE) &&
- /* GFX9 needs LS or ES for compilation, which we don't have here. */
- (sscreen->info.chip_class <= VI ||
- (sel->type != PIPE_SHADER_TESS_CTRL &&
- sel->type != PIPE_SHADER_GEOMETRY))) {
- struct si_shader_ctx_state state = {sel};
- struct si_shader_key key;
-
- memset(&key, 0, sizeof(key));
- si_parse_next_shader_property(&sel->info,
- sel->so.num_outputs != 0,
- &key);
-
- /* GFX9 doesn't have LS and ES. */
- if (sscreen->info.chip_class >= GFX9) {
- key.as_ls = 0;
- key.as_es = 0;
- }
-
- /* Set reasonable defaults, so that the shader key doesn't
- * cause any code to be eliminated.
- */
- switch (sel->type) {
- case PIPE_SHADER_TESS_CTRL:
- key.part.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
- break;
- case PIPE_SHADER_FRAGMENT:
- key.part.ps.prolog.bc_optimize_for_persp =
- sel->info.uses_persp_center &&
- sel->info.uses_persp_centroid;
- key.part.ps.prolog.bc_optimize_for_linear =
- sel->info.uses_linear_center &&
- sel->info.uses_linear_centroid;
- key.part.ps.epilog.alpha_func = PIPE_FUNC_ALWAYS;
- for (i = 0; i < 8; i++)
- if (sel->info.colors_written & (1 << i))
- key.part.ps.epilog.spi_shader_col_format |=
- V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
- break;
- }
-
- if (si_shader_select_with_key(sscreen, &state,
- &sel->compiler_ctx_state, &key,
- thread_index))
- fprintf(stderr, "radeonsi: can't create a monolithic shader\n");
- }
-
/* The GS copy shader is always pre-compiled. */
if (sel->type == PIPE_SHADER_GEOMETRY) {
- sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, tm, sel, debug);
+ sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
if (!sel->gs_copy_shader) {
fprintf(stderr, "radeonsi: can't create GS copy shader\n");
return;
}
}
+void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
+ struct util_queue_fence *ready_fence,
+ struct si_compiler_ctx_state *compiler_ctx_state,
+ void *job, util_queue_execute_func execute)
+{
+ util_queue_fence_init(ready_fence);
+
+ struct util_async_debug_callback async_debug;
+ bool wait =
+ (sctx->debug.debug_message && !sctx->debug.async) ||
+ sctx->is_debug ||
+ si_can_dump_shader(sctx->screen, processor);
+
+ if (wait) {
+ u_async_debug_init(&async_debug);
+ compiler_ctx_state->debug = async_debug.base;
+ }
+
+ util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
+ ready_fence, execute, NULL);
+
+ if (wait) {
+ util_queue_fence_wait(ready_fence);
+ u_async_debug_drain(&async_debug, &sctx->debug);
+ u_async_debug_cleanup(&async_debug);
+ }
+}
+
/* Return descriptor slot usage masks from the given shader info. */
void si_get_active_slot_masks(const struct tgsi_shader_info *info,
uint32_t *const_and_shader_buffers,
sel->nir = state->ir.nir;
si_nir_scan_shader(sel->nir, &sel->info);
+ si_nir_scan_tess_ctrl(sel->nir, &sel->info, &sel->tcs_info);
si_lower_nir(sel);
}
/* fall through */
default:
sel->outputs_written |=
- 1ull << si_shader_io_get_unique_index(name, index);
+ 1ull << si_shader_io_get_unique_index(name, index, false);
+ sel->outputs_written_before_ps |=
+ 1ull << si_shader_io_get_unique_index(name, index, true);
break;
- case TGSI_SEMANTIC_CLIPVERTEX: /* ignore these */
case TGSI_SEMANTIC_EDGEFLAG:
break;
}
/* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
* conflicts, i.e. each vertex will start at a different bank.
*/
- if (sctx->b.chip_class >= GFX9)
+ if (sctx->chip_class >= GFX9)
sel->esgs_itemsize += 4;
+
+ assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
break;
case PIPE_SHADER_FRAGMENT:
/* fall through */
default:
sel->inputs_read |=
- 1ull << si_shader_io_get_unique_index(name, index);
+ 1ull << si_shader_io_get_unique_index(name, index, true);
break;
case TGSI_SEMANTIC_PCOORD: /* ignore this */
break;
}
(void) mtx_init(&sel->mutex, mtx_plain);
- util_queue_fence_init(&sel->ready);
-
- struct util_async_debug_callback async_debug;
- bool wait =
- (sctx->debug.debug_message && !sctx->debug.async) ||
- sctx->is_debug ||
- si_can_dump_shader(sscreen, sel->info.processor);
-
- if (wait) {
- u_async_debug_init(&async_debug);
- sel->compiler_ctx_state.debug = async_debug.base;
- }
-
- util_queue_add_job(&sscreen->shader_compiler_queue, sel,
- &sel->ready, si_init_shader_selector_async,
- NULL);
-
- if (wait) {
- util_queue_fence_wait(&sel->ready);
- u_async_debug_drain(&async_debug, &sctx->debug);
- u_async_debug_cleanup(&async_debug);
- }
+ si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
+ &sel->compiler_ctx_state, sel,
+ si_init_shader_selector_async);
return sel;
}
!next_hw_vs_variant ||
old_hw_vs_variant->key.opt.clip_disable !=
next_hw_vs_variant->key.opt.clip_disable))
- si_mark_atom_dirty(sctx, &sctx->clip_regs);
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
}
static void si_update_common_shader_state(struct si_context *sctx)
if (!old_sel ||
old_sel->info.colors_written != sel->info.colors_written)
- si_mark_atom_dirty(sctx, &sctx->cb_render_state);
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
if (sctx->screen->has_out_of_order_rast &&
(!old_sel ||
old_sel->info.writes_memory != sel->info.writes_memory ||
old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
- si_mark_atom_dirty(sctx, &sctx->msaa_config);
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
}
si_set_active_descriptors_for_shader(sctx, sel);
+ si_update_ps_colorbuf0_slot(sctx);
}
static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
switch (shader->selector->type) {
case PIPE_SHADER_VERTEX:
if (shader->key.as_ls) {
- assert(sctx->b.chip_class <= VI);
+ assert(sctx->chip_class <= VI);
si_pm4_delete_state(sctx, ls, shader->pm4);
} else if (shader->key.as_es) {
- assert(sctx->b.chip_class <= VI);
+ assert(sctx->chip_class <= VI);
si_pm4_delete_state(sctx, es, shader->pm4);
} else {
si_pm4_delete_state(sctx, vs, shader->pm4);
break;
case PIPE_SHADER_TESS_EVAL:
if (shader->key.as_es) {
- assert(sctx->b.chip_class <= VI);
+ assert(sctx->chip_class <= VI);
si_pm4_delete_state(sctx, es, shader->pm4);
} else {
si_pm4_delete_state(sctx, vs, shader->pm4);
return ps_input_cntl;
}
-static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
+static void si_emit_spi_map(struct si_context *sctx)
{
- struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
struct si_shader *ps = sctx->ps_shader.current;
struct si_shader *vs = si_get_vs_state(sctx);
struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
unsigned i, num_interp, num_written = 0, bcol_interp[2];
+ unsigned spi_ps_input_cntl[32];
if (!ps || !ps->selector->info.num_inputs)
return;
num_interp = si_get_ps_num_interp(ps);
assert(num_interp > 0);
- radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
for (i = 0; i < psinfo->num_inputs; i++) {
unsigned name = psinfo->input_semantic_name[i];
unsigned index = psinfo->input_semantic_index[i];
unsigned interpolate = psinfo->input_interpolate[i];
- radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
- interpolate));
- num_written++;
+ spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
+ index, interpolate);
if (name == TGSI_SEMANTIC_COLOR) {
assert(index < ARRAY_SIZE(bcol_interp));
if (!(psinfo->colors_read & (0xf << (i * 4))))
continue;
- radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
- i, bcol_interp[i]));
- num_written++;
+ spi_ps_input_cntl[num_written++] =
+ si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
+
}
}
assert(num_interp == num_written);
+
+ /* R_028644_SPI_PS_INPUT_CNTL_0 */
+ /* Dota 2: Only ~16% of SPI map updates set different values. */
+ /* Talos: Only ~9% of SPI map updates set different values. */
+ radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
+ spi_ps_input_cntl,
+ sctx->tracked_regs.spi_ps_input_cntl, num_interp);
}
/**
/* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
* On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
*/
- unsigned gs_vertex_reuse = (sctx->b.chip_class >= VI ? 32 : 16) * num_se;
+ unsigned gs_vertex_reuse = (sctx->chip_class >= VI ? 32 : 16) * num_se;
unsigned alignment = 256 * num_se;
/* The maximum size is 63.999 MB per SE. */
unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
*
* GFX9 doesn't have the ESGS ring.
*/
- bool update_esgs = sctx->b.chip_class <= VI &&
+ bool update_esgs = sctx->chip_class <= VI &&
esgs_ring_size &&
(!sctx->esgs_ring ||
sctx->esgs_ring->width0 < esgs_ring_size);
if (update_esgs) {
pipe_resource_reference(&sctx->esgs_ring, NULL);
sctx->esgs_ring =
- si_aligned_buffer_create(sctx->b.b.screen,
- R600_RESOURCE_FLAG_UNMAPPABLE,
+ pipe_aligned_buffer_create(sctx->b.screen,
+ SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
esgs_ring_size, alignment);
if (!sctx->esgs_ring)
if (update_gsvs) {
pipe_resource_reference(&sctx->gsvs_ring, NULL);
sctx->gsvs_ring =
- si_aligned_buffer_create(sctx->b.b.screen,
- R600_RESOURCE_FLAG_UNMAPPABLE,
+ pipe_aligned_buffer_create(sctx->b.screen,
+ SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
gsvs_ring_size, alignment);
if (!sctx->gsvs_ring)
if (!pm4)
return false;
- if (sctx->b.chip_class >= CIK) {
+ if (sctx->chip_class >= CIK) {
if (sctx->esgs_ring) {
- assert(sctx->b.chip_class <= VI);
+ assert(sctx->chip_class <= VI);
si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
sctx->esgs_ring->width0 / 256);
}
}
/* Flush the context to re-emit both init_config states. */
- sctx->b.initial_gfx_cs_size = 0; /* force flush */
- si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
+ sctx->initial_gfx_cs_size = 0; /* force flush */
+ si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
/* Set ring bindings. */
if (sctx->esgs_ring) {
- assert(sctx->b.chip_class <= VI);
- si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
+ assert(sctx->chip_class <= VI);
+ si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
sctx->esgs_ring, 0, sctx->esgs_ring->width0,
true, true, 4, 64, 0);
- si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS,
+ si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
sctx->esgs_ring, 0, sctx->esgs_ring->width0,
false, false, 0, 0, 0);
}
if (sctx->gsvs_ring) {
- si_set_ring_buffer(&sctx->b.b, SI_RING_GSVS,
+ si_set_ring_buffer(sctx, SI_RING_GSVS,
sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
false, false, 0, 0, 0);
}
/* Create a bigger scratch buffer */
r600_resource_reference(&sctx->scratch_buffer, NULL);
- sctx->scratch_buffer = (struct r600_resource*)
+ sctx->scratch_buffer =
si_aligned_buffer_create(&sctx->screen->b,
- R600_RESOURCE_FLAG_UNMAPPABLE,
+ SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
scratch_needed_size, 256);
if (!sctx->scratch_buffer)
return false;
- si_mark_atom_dirty(sctx, &sctx->scratch_state);
- si_context_add_resource_size(&sctx->b.b,
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
+ si_context_add_resource_size(sctx,
&sctx->scratch_buffer->b.b);
}
S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
if (spi_tmpring_size != sctx->spi_tmpring_size) {
sctx->spi_tmpring_size = spi_tmpring_size;
- si_mark_atom_dirty(sctx, &sctx->scratch_state);
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
}
return true;
}
static void si_init_tess_factor_ring(struct si_context *sctx)
{
- bool double_offchip_buffers = sctx->b.chip_class >= CIK &&
- sctx->b.family != CHIP_CARRIZO &&
- sctx->b.family != CHIP_STONEY;
- /* This must be one less than the maximum number due to a hw limitation.
- * Various hardware bugs in SI, CIK, and GFX9 need this.
- */
- unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
- unsigned max_offchip_buffers = max_offchip_buffers_per_se *
- sctx->screen->info.max_se;
- unsigned offchip_granularity;
+ assert(!sctx->tess_rings);
- switch (sctx->screen->tess_offchip_block_dw_size) {
- default:
- assert(0);
- /* fall through */
- case 8192:
- offchip_granularity = V_03093C_X_8K_DWORDS;
- break;
- case 4096:
- offchip_granularity = V_03093C_X_4K_DWORDS;
- break;
- }
-
- assert(!sctx->tf_ring);
- /* Use 64K alignment for both rings, so that we can pass the address
- * to shaders as one SGPR containing bits [16:47].
+ /* The address must be aligned to 2^19, because the shader only
+ * receives the high 13 bits.
*/
- sctx->tf_ring = si_aligned_buffer_create(sctx->b.b.screen,
- R600_RESOURCE_FLAG_UNMAPPABLE,
- PIPE_USAGE_DEFAULT,
- 32768 * sctx->screen->info.max_se,
- 64 * 1024);
- if (!sctx->tf_ring)
- return;
-
- assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
-
- sctx->tess_offchip_ring =
- si_aligned_buffer_create(sctx->b.b.screen,
- R600_RESOURCE_FLAG_UNMAPPABLE,
- PIPE_USAGE_DEFAULT,
- max_offchip_buffers *
- sctx->screen->tess_offchip_block_dw_size * 4,
- 64 * 1024);
- if (!sctx->tess_offchip_ring)
+ sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
+ SI_RESOURCE_FLAG_32BIT,
+ PIPE_USAGE_DEFAULT,
+ sctx->screen->tess_offchip_ring_size +
+ sctx->screen->tess_factor_ring_size,
+ 1 << 19);
+ if (!sctx->tess_rings)
return;
si_init_config_add_vgt_flush(sctx);
- uint64_t offchip_va = r600_resource(sctx->tess_offchip_ring)->gpu_address;
- uint64_t factor_va = r600_resource(sctx->tf_ring)->gpu_address;
- assert((offchip_va & 0xffff) == 0);
- assert((factor_va & 0xffff) == 0);
-
- si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tess_offchip_ring),
- RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
- si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tf_ring),
+ si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tess_rings),
RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
- /* Append these registers to the init config state. */
- if (sctx->b.chip_class >= CIK) {
- if (sctx->b.chip_class >= VI)
- --max_offchip_buffers;
+ uint64_t factor_va = r600_resource(sctx->tess_rings)->gpu_address +
+ sctx->screen->tess_offchip_ring_size;
+ /* Append these registers to the init config state. */
+ if (sctx->chip_class >= CIK) {
si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
- S_030938_SIZE(sctx->tf_ring->width0 / 4));
+ S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
factor_va >> 8);
- if (sctx->b.chip_class >= GFX9)
+ if (sctx->chip_class >= GFX9)
si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
- factor_va >> 40);
+ S_030944_BASE_HI(factor_va >> 40));
si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
- S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
- S_03093C_OFFCHIP_GRANULARITY(offchip_granularity));
+ sctx->screen->vgt_hs_offchip_param);
} else {
- assert(offchip_granularity == V_03093C_X_8K_DWORDS);
si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
- S_008988_SIZE(sctx->tf_ring->width0 / 4));
+ S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
factor_va >> 8);
si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
- S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers));
- }
-
- if (sctx->b.chip_class >= GFX9) {
- si_pm4_set_reg(sctx->init_config,
- R_00B430_SPI_SHADER_USER_DATA_LS_0 +
- GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K * 4,
- offchip_va >> 16);
- si_pm4_set_reg(sctx->init_config,
- R_00B430_SPI_SHADER_USER_DATA_LS_0 +
- GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K * 4,
- factor_va >> 16);
- } else {
- si_pm4_set_reg(sctx->init_config,
- R_00B430_SPI_SHADER_USER_DATA_HS_0 +
- GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K * 4,
- offchip_va >> 16);
- si_pm4_set_reg(sctx->init_config,
- R_00B430_SPI_SHADER_USER_DATA_HS_0 +
- GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K * 4,
- factor_va >> 16);
+ sctx->screen->vgt_hs_offchip_param);
}
/* Flush the context to re-emit the init_config state.
* This is done only once in a lifetime of a context.
*/
si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
- sctx->b.initial_gfx_cs_size = 0; /* force flush */
- si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
+ sctx->initial_gfx_cs_size = 0; /* force flush */
+ si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
}
/**
ureg_END(ureg);
sctx->fixed_func_tcs_shader.cso =
- ureg_create_shader_and_destroy(ureg, &sctx->b.b);
+ ureg_create_shader_and_destroy(ureg, &sctx->b);
}
static void si_update_vgt_shader_config(struct si_context *sctx)
S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
}
- if (sctx->b.chip_class >= GFX9)
+ if (sctx->chip_class >= GFX9)
stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
int r;
- compiler_state.tm = sctx->tm;
+ compiler_state.compiler = &sctx->compiler;
compiler_state.debug = sctx->debug;
compiler_state.is_debug_context = sctx->is_debug;
/* Update stages before GS. */
if (sctx->tes_shader.cso) {
- if (!sctx->tf_ring) {
+ if (!sctx->tess_rings) {
si_init_tess_factor_ring(sctx);
- if (!sctx->tf_ring)
+ if (!sctx->tess_rings)
return false;
}
/* VS as LS */
- if (sctx->b.chip_class <= VI) {
+ if (sctx->chip_class <= VI) {
r = si_shader_select(ctx, &sctx->vs_shader,
&compiler_state);
if (r)
if (sctx->gs_shader.cso) {
/* TES as ES */
- if (sctx->b.chip_class <= VI) {
+ if (sctx->chip_class <= VI) {
r = si_shader_select(ctx, &sctx->tes_shader,
&compiler_state);
if (r)
si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
}
} else if (sctx->gs_shader.cso) {
- if (sctx->b.chip_class <= VI) {
+ if (sctx->chip_class <= VI) {
/* VS as ES */
r = si_shader_select(ctx, &sctx->vs_shader,
&compiler_state);
return false;
} else {
si_pm4_bind_state(sctx, gs, NULL);
- if (sctx->b.chip_class <= VI)
+ if (sctx->chip_class <= VI)
si_pm4_bind_state(sctx, es, NULL);
}
si_update_vgt_shader_config(sctx);
if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
- si_mark_atom_dirty(sctx, &sctx->clip_regs);
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
if (sctx->ps_shader.cso) {
unsigned db_shader_control;
sctx->flatshade != rs->flatshade) {
sctx->sprite_coord_enable = rs->sprite_coord_enable;
sctx->flatshade = rs->flatshade;
- si_mark_atom_dirty(sctx, &sctx->spi_map);
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
}
if (sctx->screen->rbplus_allowed &&
(!old_ps ||
old_spi_shader_col_format !=
sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
- si_mark_atom_dirty(sctx, &sctx->cb_render_state);
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
if (sctx->ps_db_shader_control != db_shader_control) {
sctx->ps_db_shader_control = db_shader_control;
- si_mark_atom_dirty(sctx, &sctx->db_render_state);
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
if (sctx->screen->dpbb_allowed)
- si_mark_atom_dirty(sctx, &sctx->dpbb_state);
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
}
if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
- si_mark_atom_dirty(sctx, &sctx->msaa_config);
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
- if (sctx->b.chip_class == SI)
- si_mark_atom_dirty(sctx, &sctx->db_render_state);
+ if (sctx->chip_class == SI)
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
if (sctx->framebuffer.nr_samples <= 1)
- si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
}
}
return false;
}
- if (sctx->b.chip_class >= CIK) {
+ if (sctx->chip_class >= CIK) {
if (si_pm4_state_enabled_and_changed(sctx, ls))
sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
else if (!sctx->queued.named.ls)
return true;
}
-static void si_emit_scratch_state(struct si_context *sctx,
- struct r600_atom *atom)
+static void si_emit_scratch_state(struct si_context *sctx)
{
- struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
+ struct radeon_cmdbuf *cs = sctx->gfx_cs;
radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
sctx->spi_tmpring_size);
if (sctx->scratch_buffer) {
- radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
+ radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
sctx->scratch_buffer, RADEON_USAGE_READWRITE,
RADEON_PRIO_SCRATCH_BUFFER);
}
void *si_get_blit_vs(struct si_context *sctx, enum blitter_attrib_type type,
unsigned num_layers)
{
- struct pipe_context *pipe = &sctx->b.b;
unsigned vs_blit_property;
void **vs;
}
ureg_END(ureg);
- *vs = ureg_create_shader_and_destroy(ureg, pipe);
+ *vs = ureg_create_shader_and_destroy(ureg, &sctx->b);
return *vs;
}
void si_init_shader_functions(struct si_context *sctx)
{
- si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
- si_init_atom(sctx, &sctx->scratch_state, &sctx->atoms.s.scratch_state,
- si_emit_scratch_state);
-
- sctx->b.b.create_vs_state = si_create_shader_selector;
- sctx->b.b.create_tcs_state = si_create_shader_selector;
- sctx->b.b.create_tes_state = si_create_shader_selector;
- sctx->b.b.create_gs_state = si_create_shader_selector;
- sctx->b.b.create_fs_state = si_create_shader_selector;
-
- sctx->b.b.bind_vs_state = si_bind_vs_shader;
- sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
- sctx->b.b.bind_tes_state = si_bind_tes_shader;
- sctx->b.b.bind_gs_state = si_bind_gs_shader;
- sctx->b.b.bind_fs_state = si_bind_ps_shader;
-
- sctx->b.b.delete_vs_state = si_delete_shader_selector;
- sctx->b.b.delete_tcs_state = si_delete_shader_selector;
- sctx->b.b.delete_tes_state = si_delete_shader_selector;
- sctx->b.b.delete_gs_state = si_delete_shader_selector;
- sctx->b.b.delete_fs_state = si_delete_shader_selector;
+ sctx->atoms.s.spi_map.emit = si_emit_spi_map;
+ sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
+
+ sctx->b.create_vs_state = si_create_shader_selector;
+ sctx->b.create_tcs_state = si_create_shader_selector;
+ sctx->b.create_tes_state = si_create_shader_selector;
+ sctx->b.create_gs_state = si_create_shader_selector;
+ sctx->b.create_fs_state = si_create_shader_selector;
+
+ sctx->b.bind_vs_state = si_bind_vs_shader;
+ sctx->b.bind_tcs_state = si_bind_tcs_shader;
+ sctx->b.bind_tes_state = si_bind_tes_shader;
+ sctx->b.bind_gs_state = si_bind_gs_shader;
+ sctx->b.bind_fs_state = si_bind_ps_shader;
+
+ sctx->b.delete_vs_state = si_delete_shader_selector;
+ sctx->b.delete_tcs_state = si_delete_shader_selector;
+ sctx->b.delete_tes_state = si_delete_shader_selector;
+ sctx->b.delete_gs_state = si_delete_shader_selector;
+ sctx->b.delete_fs_state = si_delete_shader_selector;
}
projects / mesa.git / blobdiff