freedreno/a6xx: fix border-color swizzles

[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index ad7d21e78167773c886e81ce544b9ddfd790d5a6..5bdfd4f6ac11561c4b5d044378e5d49048c7483b 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -337,10 +337,10 @@ void si_destroy_shader_cache(struct si_screen *sscreen)
 /* SHADER STATES */
 
 static void si_set_tesseval_regs(struct si_screen *sscreen,
-                                struct si_shader_selector *tes,
+                                const struct si_shader_selector *tes,
                                 struct si_pm4_state *pm4)
 {
-       struct tgsi_shader_info *info = &tes->info;
+       const struct tgsi_shader_info *info = &tes->info;
        unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
        unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
        bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
@@ -464,12 +464,7 @@ static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
 {
        /* Add the pointer to VBO descriptors. */
-       if (HAVE_32BIT_POINTERS) {
-               return num_always_on_user_sgprs + 1;
-       } else {
-               assert(num_always_on_user_sgprs % 2 == 0);
-               return num_always_on_user_sgprs + 2;
-       }
+       return num_always_on_user_sgprs + 1;
 }
 
 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
@@ -1662,7 +1657,7 @@ static inline void si_shader_selector_key(struct pipe_context *ctx,
                key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
 
                /* ps_uses_fbfetch is true only if the color buffer is bound. */
-               if (sctx->ps_uses_fbfetch) {
+               if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
                        struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
                        struct pipe_resource *tex = cb0->texture;
 
@@ -2048,6 +2043,9 @@ static void si_init_shader_selector_async(void *job, int thread_index)
        assert(thread_index < ARRAY_SIZE(sscreen->compiler));
        compiler = &sscreen->compiler[thread_index];
 
+       if (sel->nir)
+               si_lower_nir(sel);
+
        /* Compile the main shader part for use with a prolog and/or epilog.
         * If this fails, the driver will try to compile a monolithic shader
         * on demand.
@@ -2243,9 +2241,7 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
                sel->nir = state->ir.nir;
 
                si_nir_scan_shader(sel->nir, &sel->info);
-               si_nir_scan_tess_ctrl(sel->nir, &sel->info, &sel->tcs_info);
-
-               si_lower_nir(sel);
+               si_nir_scan_tess_ctrl(sel->nir, &sel->tcs_info);
        }
 
        sel->type = sel->info.processor;
@@ -3094,7 +3090,7 @@ static int si_update_scratch_buffer(struct si_context *sctx,
        /* Update the shader state to use the new shader bo. */
        si_shader_init_pm4_state(sctx->screen, shader);
 
-       r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
+       si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
 
        si_shader_unlock(shader);
        return 1;
@@ -3204,7 +3200,7 @@ static bool si_update_spi_tmpring_size(struct si_context *sctx)
        if (scratch_needed_size > 0) {
                if (scratch_needed_size > current_scratch_buffer_size) {
                        /* Create a bigger scratch buffer */
-                       r600_resource_reference(&sctx->scratch_buffer, NULL);
+                       si_resource_reference(&sctx->scratch_buffer, NULL);
 
                        sctx->scratch_buffer =
                                si_aligned_buffer_create(&sctx->screen->b,
@@ -3254,10 +3250,10 @@ static void si_init_tess_factor_ring(struct si_context *sctx)
 
        si_init_config_add_vgt_flush(sctx);
 
-       si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tess_rings),
+       si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
                      RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
 
-       uint64_t factor_va = r600_resource(sctx->tess_rings)->gpu_address +
+       uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
                             sctx->screen->tess_offchip_ring_size;
 
        /* Append these registers to the init config state. */