radeonsi: don't leak an index buffer if draw_vbo fails

[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index f751906c6d6a90c099e1002a3137a6ab9cb80dd9..9e052e1efcefdc139c1aff03f1da741772808c6b 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -1657,7 +1657,7 @@ static inline void si_shader_selector_key(struct pipe_context *ctx,
                key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
 
                /* ps_uses_fbfetch is true only if the color buffer is bound. */
-               if (sctx->ps_uses_fbfetch) {
+               if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
                        struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
                        struct pipe_resource *tex = cb0->texture;
 
@@ -2238,7 +2238,7 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
                sel->nir = state->ir.nir;
 
                si_nir_scan_shader(sel->nir, &sel->info);
-               si_nir_scan_tess_ctrl(sel->nir, &sel->info, &sel->tcs_info);
+               si_nir_scan_tess_ctrl(sel->nir, &sel->tcs_info);
 
                si_lower_nir(sel);
        }
@@ -3089,7 +3089,7 @@ static int si_update_scratch_buffer(struct si_context *sctx,
        /* Update the shader state to use the new shader bo. */
        si_shader_init_pm4_state(sctx->screen, shader);
 
-       r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
+       si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
 
        si_shader_unlock(shader);
        return 1;
@@ -3199,7 +3199,7 @@ static bool si_update_spi_tmpring_size(struct si_context *sctx)
        if (scratch_needed_size > 0) {
                if (scratch_needed_size > current_scratch_buffer_size) {
                        /* Create a bigger scratch buffer */
-                       r600_resource_reference(&sctx->scratch_buffer, NULL);
+                       si_resource_reference(&sctx->scratch_buffer, NULL);
 
                        sctx->scratch_buffer =
                                si_aligned_buffer_create(&sctx->screen->b,
@@ -3249,10 +3249,10 @@ static void si_init_tess_factor_ring(struct si_context *sctx)
 
        si_init_config_add_vgt_flush(sctx);
 
-       si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tess_rings),
+       si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
                      RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
 
-       uint64_t factor_va = r600_resource(sctx->tess_rings)->gpu_address +
+       uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
                             sctx->screen->tess_offchip_ring_size;
 
        /* Append these registers to the init config state. */