*/
#include "si_pipe.h"
-#include "si_shader.h"
#include "sid.h"
#include "radeon/r600_cs.h"
#include "tgsi/tgsi_parse.h"
#include "tgsi/tgsi_ureg.h"
#include "util/hash_table.h"
-#include "util/u_hash.h"
+#include "util/crc32.h"
#include "util/u_memory.h"
#include "util/u_prim.h"
-#include "util/u_simple_shaders.h"
+
+#include "util/disk_cache.h"
+#include "util/mesa-sha1.h"
/* SHADER_CACHE */
{
*size = *ptr++;
assert(*data == NULL);
+ if (!*size)
+ return ptr;
*data = malloc(*size);
return read_data(ptr, *data, *size);
}
unsigned relocs_size = shader->binary.reloc_count *
sizeof(shader->binary.relocs[0]);
unsigned disasm_size = strlen(shader->binary.disasm_string) + 1;
+ unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
+ strlen(shader->binary.llvm_ir_string) + 1 : 0;
unsigned size =
4 + /* total size */
4 + /* CRC32 of the data below */
4 + align(shader->binary.code_size, 4) +
4 + align(shader->binary.rodata_size, 4) +
4 + align(relocs_size, 4) +
- 4 + align(disasm_size, 4);
+ 4 + align(disasm_size, 4) +
+ 4 + align(llvm_ir_size, 4);
void *buffer = CALLOC(1, size);
uint32_t *ptr = (uint32_t*)buffer;
ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
+ ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
assert((char *)ptr - (char *)buffer == size);
/* Compute CRC32. */
ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
+ ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
return true;
}
*/
static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
void *tgsi_binary,
- struct si_shader *shader)
+ struct si_shader *shader,
+ bool insert_into_disk_cache)
{
- void *hw_binary = si_get_shader_binary(shader);
+ void *hw_binary;
+ struct hash_entry *entry;
+ uint8_t key[CACHE_KEY_SIZE];
+
+ entry = _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
+ if (entry)
+ return false; /* already added */
+ hw_binary = si_get_shader_binary(shader);
if (!hw_binary)
return false;
return false;
}
+ if (sscreen->b.disk_shader_cache && insert_into_disk_cache) {
+ _mesa_sha1_compute(tgsi_binary, *((uint32_t *)tgsi_binary), key);
+ disk_cache_put(sscreen->b.disk_shader_cache, key, hw_binary,
+ *((uint32_t *) hw_binary));
+ }
+
return true;
}
{
struct hash_entry *entry =
_mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
- if (!entry)
- return false;
+ if (!entry) {
+ if (sscreen->b.disk_shader_cache) {
+ unsigned char sha1[CACHE_KEY_SIZE];
+ size_t tg_size = *((uint32_t *) tgsi_binary);
+
+ _mesa_sha1_compute(tgsi_binary, tg_size, sha1);
+
+ size_t binary_size;
+ uint8_t *buffer =
+ disk_cache_get(sscreen->b.disk_shader_cache,
+ sha1, &binary_size);
+ if (!buffer)
+ return false;
+
+ if (binary_size < sizeof(uint32_t) ||
+ *((uint32_t*)buffer) != binary_size) {
+ /* Something has gone wrong discard the item
+ * from the cache and rebuild/link from
+ * source.
+ */
+ assert(!"Invalid radeonsi shader disk cache "
+ "item!");
+
+ disk_cache_remove(sscreen->b.disk_shader_cache,
+ sha1);
+ free(buffer);
+
+ return false;
+ }
- return si_load_shader_binary(shader, entry->data);
+ if (!si_load_shader_binary(shader, buffer)) {
+ free(buffer);
+ return false;
+ }
+ free(buffer);
+
+ if (!si_shader_cache_insert_shader(sscreen, tgsi_binary,
+ shader, false))
+ FREE(tgsi_binary);
+ } else {
+ return false;
+ }
+ } else {
+ if (si_load_shader_binary(shader, entry->data))
+ FREE(tgsi_binary);
+ else
+ return false;
+ }
+ p_atomic_inc(&sscreen->b.num_shader_cache_hits);
+ return true;
}
static uint32_t si_shader_cache_key_hash(const void *key)
bool si_init_shader_cache(struct si_screen *sscreen)
{
- pipe_mutex_init(sscreen->shader_cache_mutex);
+ (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
sscreen->shader_cache =
_mesa_hash_table_create(NULL,
si_shader_cache_key_hash,
si_shader_cache_key_equals);
+
return sscreen->shader_cache != NULL;
}
if (sscreen->shader_cache)
_mesa_hash_table_destroy(sscreen->shader_cache,
si_destroy_shader_cache_entry);
- pipe_mutex_destroy(sscreen->shader_cache_mutex);
+ mtx_destroy(&sscreen->shader_cache_mutex);
}
/* SHADER STATES */
-static void si_set_tesseval_regs(struct si_shader *shader,
+static void si_set_tesseval_regs(struct si_screen *sscreen,
+ struct si_shader *shader,
struct si_pm4_state *pm4)
{
struct tgsi_shader_info *info = &shader->selector->info;
unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
- unsigned type, partitioning, topology;
+ unsigned type, partitioning, topology, distribution_mode;
switch (tes_prim_mode) {
case PIPE_PRIM_LINES:
else
topology = V_028B6C_OUTPUT_TRIANGLE_CW;
+ if (sscreen->has_distributed_tess) {
+ if (sscreen->b.family == CHIP_FIJI ||
+ sscreen->b.family >= CHIP_POLARIS10)
+ distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
+ else
+ distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
+ } else
+ distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
+
si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
S_028B6C_TYPE(type) |
S_028B6C_PARTITIONING(partitioning) |
- S_028B6C_TOPOLOGY(topology));
+ S_028B6C_TOPOLOGY(topology) |
+ S_028B6C_DISTRIBUTION_MODE(distribution_mode));
+}
+
+/* Polaris needs different VTX_REUSE_DEPTH settings depending on
+ * whether the "fractional odd" tessellation spacing is used.
+ *
+ * Possible VGT configurations and which state should set the register:
+ *
+ * Reg set in | VGT shader configuration | Value
+ * ------------------------------------------------------
+ * VS as VS | VS | 30
+ * VS as ES | ES -> GS -> VS | 30
+ * TES as VS | LS -> HS -> VS | 14 or 30
+ * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
+ */
+static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
+ struct si_shader *shader,
+ struct si_pm4_state *pm4)
+{
+ unsigned type = shader->selector->type;
+
+ if (sscreen->b.family < CHIP_POLARIS10)
+ return;
+
+ /* VS as VS, or VS as ES: */
+ if ((type == PIPE_SHADER_VERTEX &&
+ !shader->key.as_ls &&
+ !shader->is_gs_copy_shader) ||
+ /* TES as VS, or TES as ES: */
+ type == PIPE_SHADER_TESS_EVAL) {
+ unsigned vtx_reuse_depth = 30;
+
+ if (type == PIPE_SHADER_TESS_EVAL &&
+ shader->selector->info.properties[TGSI_PROPERTY_TES_SPACING] ==
+ PIPE_TESS_SPACING_FRACTIONAL_ODD)
+ vtx_reuse_depth = 14;
+
+ si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
+ vtx_reuse_depth);
+ }
+}
+
+static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
+{
+ if (shader->pm4)
+ si_pm4_clear_state(shader->pm4);
+ else
+ shader->pm4 = CALLOC_STRUCT(si_pm4_state);
+
+ return shader->pm4;
}
static void si_shader_ls(struct si_shader *shader)
unsigned vgpr_comp_cnt;
uint64_t va;
- pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
+ pm4 = si_get_shader_pm4_state(shader);
if (!pm4)
return;
va = shader->bo->gpu_address;
- si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
+ si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
/* We need at least 2 components for LS.
* VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
struct si_pm4_state *pm4;
uint64_t va;
- pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
+ pm4 = si_get_shader_pm4_state(shader);
if (!pm4)
return;
va = shader->bo->gpu_address;
- si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
+ si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
}
-static void si_shader_es(struct si_shader *shader)
+static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
{
struct si_pm4_state *pm4;
unsigned num_user_sgprs;
uint64_t va;
unsigned oc_lds_en;
- pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
-
+ pm4 = si_get_shader_pm4_state(shader);
if (!pm4)
return;
va = shader->bo->gpu_address;
- si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
+ si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
if (shader->selector->type == PIPE_SHADER_VERTEX) {
vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
- si_set_tesseval_regs(shader, pm4);
+ si_set_tesseval_regs(sscreen, shader, pm4);
+
+ polaris_set_vgt_vertex_reuse(sscreen, shader, pm4);
}
/**
* Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
* geometry shader.
*/
-static uint32_t si_vgt_gs_mode(struct si_shader *shader)
+static uint32_t si_vgt_gs_mode(struct si_shader_selector *sel)
{
- unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
+ unsigned gs_max_vert_out = sel->gs_max_out_vertices;
unsigned cut_mode;
if (gs_max_vert_out <= 128) {
static void si_shader_gs(struct si_shader *shader)
{
- unsigned gs_vert_itemsize = shader->selector->gsvs_vertex_size;
- unsigned gsvs_itemsize = shader->selector->max_gsvs_emit_size >> 2;
- unsigned gs_num_invocations = shader->selector->gs_num_invocations;
+ struct si_shader_selector *sel = shader->selector;
+ const ubyte *num_components = sel->info.num_stream_output_components;
+ unsigned gs_num_invocations = sel->gs_num_invocations;
struct si_pm4_state *pm4;
uint64_t va;
- unsigned max_stream = shader->selector->max_gs_stream;
-
- /* The GSVS_RING_ITEMSIZE register takes 15 bits */
- assert(gsvs_itemsize < (1 << 15));
-
- pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
+ unsigned max_stream = sel->max_gs_stream;
+ unsigned offset;
+ pm4 = si_get_shader_pm4_state(shader);
if (!pm4)
return;
- si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(shader));
+ si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(shader->selector));
- si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
- si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize * ((max_stream >= 2) ? 2 : 1));
- si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize * ((max_stream >= 3) ? 3 : 1));
+ offset = num_components[0] * sel->gs_max_out_vertices;
+ si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, offset);
+ if (max_stream >= 1)
+ offset += num_components[1] * sel->gs_max_out_vertices;
+ si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, offset);
+ if (max_stream >= 2)
+ offset += num_components[2] * sel->gs_max_out_vertices;
+ si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, offset);
+ if (max_stream >= 3)
+ offset += num_components[3] * sel->gs_max_out_vertices;
+ si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
- si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize * (max_stream + 1));
+ /* The GSVS_RING_ITEMSIZE register takes 15 bits */
+ assert(offset < (1 << 15));
si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, shader->selector->gs_max_out_vertices);
- si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize >> 2);
- si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? gs_vert_itemsize >> 2 : 0);
- si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? gs_vert_itemsize >> 2 : 0);
- si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? gs_vert_itemsize >> 2 : 0);
+ si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, num_components[0]);
+ si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? num_components[1] : 0);
+ si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? num_components[2] : 0);
+ si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? num_components[3] : 0);
si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
S_028B90_ENABLE(gs_num_invocations > 0));
va = shader->bo->gpu_address;
- si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
+ si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
* If \p gs is non-NULL, it points to the geometry shader for which this shader
* is the copy shader.
*/
-static void si_shader_vs(struct si_shader *shader, struct si_shader *gs)
+static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
+ struct si_shader_selector *gs)
{
struct si_pm4_state *pm4;
unsigned num_user_sgprs;
shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
bool enable_prim_id = si_vs_exports_prim_id(shader);
- pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
-
+ pm4 = si_get_shader_pm4_state(shader);
if (!pm4)
return;
}
va = shader->bo->gpu_address;
- si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
+ si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
if (gs) {
vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
- si_set_tesseval_regs(shader, pm4);
+ si_set_tesseval_regs(sscreen, shader, pm4);
+
+ polaris_set_vgt_vertex_reuse(sscreen, shader, pm4);
}
static unsigned si_get_ps_num_interp(struct si_shader *ps)
unsigned num_colors = !!(info->colors_read & 0x0f) +
!!(info->colors_read & 0xf0);
unsigned num_interp = ps->selector->info.num_inputs +
- (ps->key.ps.prolog.color_two_side ? num_colors : 0);
+ (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
assert(num_interp <= 32);
return MIN2(num_interp, 32);
static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
{
- unsigned value = shader->key.ps.epilog.spi_shader_col_format;
+ unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
/* If the i-th target format is set, all previous target formats must
unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
uint64_t va;
- bool has_centroid;
unsigned input_ena = shader->config.spi_ps_input_ena;
/* we need to enable at least one of them, otherwise we hang the GPU */
G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
-
- pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
-
+ /* POS_W_FLOAT_ENA requires one of the perspective weights. */
+ assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
+ G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
+ G_0286CC_PERSP_CENTER_ENA(input_ena) ||
+ G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
+ G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
+
+ /* Validate interpolation optimization flags (read as implications). */
+ assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
+ (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
+ G_0286CC_PERSP_CENTROID_ENA(input_ena)));
+ assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
+ (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
+ G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
+ assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
+ (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
+ !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
+ assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
+ (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
+ !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
+ assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
+ (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
+ !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
+ assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
+ (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
+ !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
+
+ /* Validate cases when the optimizations are off (read as implications). */
+ assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
+ !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
+ !G_0286CC_PERSP_CENTROID_ENA(input_ena));
+ assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
+ !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
+ !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
+
+ pm4 = si_get_shader_pm4_state(shader);
if (!pm4)
return;
shader->config.spi_ps_input_addr);
/* Set interpolation controls. */
- has_centroid = G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena) ||
- G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena);
-
- spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
- S_0286D8_BC_OPTIMIZE_DISABLE(has_centroid);
+ spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
/* Set registers. */
si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
- info->writes_samplemask ? V_028710_SPI_SHADER_32_ABGR :
- info->writes_stencil ? V_028710_SPI_SHADER_32_GR :
- info->writes_z ? V_028710_SPI_SHADER_32_R :
- V_028710_SPI_SHADER_ZERO);
+ si_get_spi_shader_z_format(info->writes_z,
+ info->writes_stencil,
+ info->writes_samplemask));
si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
va = shader->bo->gpu_address;
- si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
+ si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
-
- /* Prefer RE_Z if the shader is complex enough. The requirement is either:
- * - the shader uses at least 2 VMEM instructions, or
- * - the code size is at least 50 2-dword instructions or 100 1-dword
- * instructions.
- *
- * Shaders with side effects that must execute independently of the
- * depth test require LATE_Z.
- */
- if (info->writes_memory &&
- !info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL])
- shader->z_order = V_02880C_LATE_Z;
- else if (info->num_memory_instructions >= 2 ||
- shader->binary.code_size > 100*4)
- shader->z_order = V_02880C_EARLY_Z_THEN_RE_Z;
- else
- shader->z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
}
-static void si_shader_init_pm4_state(struct si_shader *shader)
+static void si_shader_init_pm4_state(struct si_screen *sscreen,
+ struct si_shader *shader)
{
-
- if (shader->pm4)
- si_pm4_free_state_simple(shader->pm4);
-
switch (shader->selector->type) {
case PIPE_SHADER_VERTEX:
- if (shader->key.vs.as_ls)
+ if (shader->key.as_ls)
si_shader_ls(shader);
- else if (shader->key.vs.as_es)
- si_shader_es(shader);
+ else if (shader->key.as_es)
+ si_shader_es(sscreen, shader);
else
- si_shader_vs(shader, NULL);
+ si_shader_vs(sscreen, shader, NULL);
break;
case PIPE_SHADER_TESS_CTRL:
si_shader_hs(shader);
break;
case PIPE_SHADER_TESS_EVAL:
- if (shader->key.tes.as_es)
- si_shader_es(shader);
+ if (shader->key.as_es)
+ si_shader_es(sscreen, shader);
else
- si_shader_vs(shader, NULL);
+ si_shader_vs(sscreen, shader, NULL);
break;
case PIPE_SHADER_GEOMETRY:
si_shader_gs(shader);
- si_shader_vs(shader->gs_copy_shader, shader);
break;
case PIPE_SHADER_FRAGMENT:
si_shader_ps(shader);
static unsigned si_get_alpha_test_func(struct si_context *sctx)
{
/* Alpha-test should be disabled if colorbuffer 0 is integer. */
- if (sctx->queued.named.dsa &&
- !sctx->framebuffer.cb0_is_integer)
+ if (sctx->queued.named.dsa)
return sctx->queued.named.dsa->alpha_func;
return PIPE_FUNC_ALWAYS;
}
+static void si_shader_selector_key_hw_vs(struct si_context *sctx,
+ struct si_shader_selector *vs,
+ struct si_shader_key *key)
+{
+ struct si_shader_selector *ps = sctx->ps_shader.cso;
+
+ key->opt.hw_vs.clip_disable =
+ sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
+ (vs->info.clipdist_writemask ||
+ vs->info.writes_clipvertex) &&
+ !vs->info.culldist_writemask;
+
+ /* Find out if PS is disabled. */
+ bool ps_disabled = true;
+ if (ps) {
+ bool ps_modifies_zs = ps->info.uses_kill ||
+ ps->info.writes_z ||
+ ps->info.writes_stencil ||
+ ps->info.writes_samplemask ||
+ si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
+
+ unsigned ps_colormask = sctx->framebuffer.colorbuf_enabled_4bit &
+ sctx->queued.named.blend->cb_target_mask;
+ if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
+ ps_colormask &= ps->colors_written_4bit;
+
+ ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
+ (!ps_colormask &&
+ !ps_modifies_zs &&
+ !ps->info.writes_memory);
+ }
+
+ /* Find out which VS outputs aren't used by the PS. */
+ uint64_t outputs_written = vs->outputs_written;
+ uint32_t outputs_written2 = vs->outputs_written2;
+ uint64_t inputs_read = 0;
+ uint32_t inputs_read2 = 0;
+
+ outputs_written &= ~0x3; /* ignore POSITION, PSIZE */
+
+ if (!ps_disabled) {
+ inputs_read = ps->inputs_read;
+ inputs_read2 = ps->inputs_read2;
+ }
+
+ uint64_t linked = outputs_written & inputs_read;
+ uint32_t linked2 = outputs_written2 & inputs_read2;
+
+ key->opt.hw_vs.kill_outputs = ~linked & outputs_written;
+ key->opt.hw_vs.kill_outputs2 = ~linked2 & outputs_written2;
+}
+
/* Compute the key for the hw shader variant */
static inline void si_shader_selector_key(struct pipe_context *ctx,
struct si_shader_selector *sel,
- union si_shader_key *key)
+ struct si_shader_key *key)
{
struct si_context *sctx = (struct si_context *)ctx;
unsigned i;
unsigned count = MIN2(sel->info.num_inputs,
sctx->vertex_elements->count);
for (i = 0; i < count; ++i)
- key->vs.prolog.instance_divisors[i] =
+ key->part.vs.prolog.instance_divisors[i] =
sctx->vertex_elements->elements[i].instance_divisor;
+
+ memcpy(key->mono.vs.fix_fetch,
+ sctx->vertex_elements->fix_fetch, count);
}
if (sctx->tes_shader.cso)
- key->vs.as_ls = 1;
+ key->as_ls = 1;
else if (sctx->gs_shader.cso)
- key->vs.as_es = 1;
+ key->as_es = 1;
+ else {
+ si_shader_selector_key_hw_vs(sctx, sel, key);
- if (!sctx->gs_shader.cso && sctx->ps_shader.cso &&
- sctx->ps_shader.cso->info.uses_primid)
- key->vs.epilog.export_prim_id = 1;
+ if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
+ key->part.vs.epilog.export_prim_id = 1;
+ }
break;
case PIPE_SHADER_TESS_CTRL:
- key->tcs.epilog.prim_mode =
+ key->part.tcs.epilog.prim_mode =
sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
+ key->part.tcs.epilog.tes_reads_tess_factors =
+ sctx->tes_shader.cso->info.reads_tess_factors;
+
+ if (sel == sctx->fixed_func_tcs_shader.cso)
+ key->mono.tcs.inputs_to_copy = sctx->vs_shader.cso->outputs_written;
break;
case PIPE_SHADER_TESS_EVAL:
if (sctx->gs_shader.cso)
- key->tes.as_es = 1;
- else if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
- key->tes.epilog.export_prim_id = 1;
+ key->as_es = 1;
+ else {
+ si_shader_selector_key_hw_vs(sctx, sel, key);
+
+ if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
+ key->part.tes.epilog.export_prim_id = 1;
+ }
break;
case PIPE_SHADER_GEOMETRY:
+ key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
break;
case PIPE_SHADER_FRAGMENT: {
struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
sel->info.colors_written == 0x1)
- key->ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
+ key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
if (blend) {
/* Select the shader color format based on whether
* blending or alpha are needed.
*/
- key->ps.epilog.spi_shader_col_format =
+ key->part.ps.epilog.spi_shader_col_format =
(blend->blend_enable_4bit & blend->need_src_alpha_4bit &
sctx->framebuffer.spi_shader_col_format_blend_alpha) |
(blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
sctx->framebuffer.spi_shader_col_format_alpha) |
(~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
sctx->framebuffer.spi_shader_col_format);
+
+ /* The output for dual source blending should have
+ * the same format as the first output.
+ */
+ if (blend->dual_src_blend)
+ key->part.ps.epilog.spi_shader_col_format |=
+ (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
} else
- key->ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
+ key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
/* If alpha-to-coverage is enabled, we have to export alpha
* even if there is no color buffer.
*/
- if (!(key->ps.epilog.spi_shader_col_format & 0xf) &&
+ if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
blend && blend->alpha_to_coverage)
- key->ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
+ key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
/* On SI and CIK except Hawaii, the CB doesn't clamp outputs
* to the range supported by the type if a channel has less
* than 16 bits and the export format is 16_ABGR.
*/
- if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII)
- key->ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
+ if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII) {
+ key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
+ key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
+ }
/* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
- if (!key->ps.epilog.last_cbuf) {
- key->ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
- key->ps.epilog.color_is_int8 &= sel->info.colors_written;
+ if (!key->part.ps.epilog.last_cbuf) {
+ key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
+ key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
+ key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
}
if (rs) {
sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
- key->ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
+ key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
+ key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
if (sctx->queued.named.blend) {
- key->ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
- rs->multisample_enable &&
- !sctx->framebuffer.cb0_is_integer;
+ key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
+ rs->multisample_enable;
}
- key->ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
- key->ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
+ key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
+ key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
(is_line && rs->line_smooth)) &&
sctx->framebuffer.nr_samples <= 1;
- key->ps.epilog.clamp_color = rs->clamp_fragment_color;
-
- key->ps.prolog.force_persample_interp =
- rs->force_persample_interp &&
- rs->multisample_enable &&
- sctx->framebuffer.nr_samples > 1 &&
- sctx->ps_iter_samples > 1 &&
- (sel->info.uses_persp_center ||
- sel->info.uses_persp_centroid ||
- sel->info.uses_linear_center ||
- sel->info.uses_linear_centroid);
+ key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
+
+ if (rs->force_persample_interp &&
+ rs->multisample_enable &&
+ sctx->framebuffer.nr_samples > 1 &&
+ sctx->ps_iter_samples > 1) {
+ key->part.ps.prolog.force_persp_sample_interp =
+ sel->info.uses_persp_center ||
+ sel->info.uses_persp_centroid;
+
+ key->part.ps.prolog.force_linear_sample_interp =
+ sel->info.uses_linear_center ||
+ sel->info.uses_linear_centroid;
+ } else if (rs->multisample_enable &&
+ sctx->framebuffer.nr_samples > 1) {
+ key->part.ps.prolog.bc_optimize_for_persp =
+ sel->info.uses_persp_center &&
+ sel->info.uses_persp_centroid;
+ key->part.ps.prolog.bc_optimize_for_linear =
+ sel->info.uses_linear_center &&
+ sel->info.uses_linear_centroid;
+ } else {
+ /* Make sure SPI doesn't compute more than 1 pair
+ * of (i,j), which is the optimization here. */
+ key->part.ps.prolog.force_persp_center_interp =
+ sel->info.uses_persp_center +
+ sel->info.uses_persp_centroid +
+ sel->info.uses_persp_sample > 1;
+
+ key->part.ps.prolog.force_linear_center_interp =
+ sel->info.uses_linear_center +
+ sel->info.uses_linear_centroid +
+ sel->info.uses_linear_sample > 1;
+ }
}
- key->ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
+ key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
break;
}
default:
}
}
+static void si_build_shader_variant(void *job, int thread_index)
+{
+ struct si_shader *shader = (struct si_shader *)job;
+ struct si_shader_selector *sel = shader->selector;
+ struct si_screen *sscreen = sel->screen;
+ LLVMTargetMachineRef tm;
+ struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
+ int r;
+
+ if (thread_index >= 0) {
+ assert(thread_index < ARRAY_SIZE(sscreen->tm));
+ tm = sscreen->tm[thread_index];
+ if (!debug->async)
+ debug = NULL;
+ } else {
+ tm = shader->compiler_ctx_state.tm;
+ }
+
+ r = si_shader_create(sscreen, tm, shader, debug);
+ if (unlikely(r)) {
+ R600_ERR("Failed to build shader variant (type=%u) %d\n",
+ sel->type, r);
+ shader->compilation_failed = true;
+ return;
+ }
+
+ if (shader->compiler_ctx_state.is_debug_context) {
+ FILE *f = open_memstream(&shader->shader_log,
+ &shader->shader_log_size);
+ if (f) {
+ si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
+ fclose(f);
+ }
+ }
+
+ si_shader_init_pm4_state(sscreen, shader);
+}
+
/* Select the hw shader variant depending on the current state. */
-static int si_shader_select_with_key(struct pipe_context *ctx,
+static int si_shader_select_with_key(struct si_screen *sscreen,
struct si_shader_ctx_state *state,
- union si_shader_key *key)
+ struct si_compiler_ctx_state *compiler_state,
+ struct si_shader_key *key,
+ int thread_index)
{
- struct si_context *sctx = (struct si_context *)ctx;
+ static const struct si_shader_key zeroed;
struct si_shader_selector *sel = state->cso;
struct si_shader *current = state->current;
struct si_shader *iter, *shader = NULL;
- int r;
+ if (unlikely(sscreen->b.debug_flags & DBG_NO_OPT_VARIANT)) {
+ memset(&key->opt, 0, sizeof(key->opt));
+ }
+
+again:
/* Check if we don't need to change anything.
* This path is also used for most shaders that don't need multiple
* variants, it will cost just a computation of the key and this
* test. */
- if (likely(current && memcmp(¤t->key, key, sizeof(*key)) == 0))
+ if (likely(current &&
+ memcmp(¤t->key, key, sizeof(*key)) == 0 &&
+ (!current->is_optimized ||
+ util_queue_fence_is_signalled(¤t->optimized_ready))))
return 0;
- pipe_mutex_lock(sel->mutex);
+ /* This must be done before the mutex is locked, because async GS
+ * compilation calls this function too, and therefore must enter
+ * the mutex first.
+ *
+ * Only wait if we are in a draw call. Don't wait if we are
+ * in a compiler thread.
+ */
+ if (thread_index < 0)
+ util_queue_fence_wait(&sel->ready);
+
+ mtx_lock(&sel->mutex);
/* Find the shader variant. */
for (iter = sel->first_variant; iter; iter = iter->next_variant) {
/* Don't check the "current" shader. We checked it above. */
if (current != iter &&
memcmp(&iter->key, key, sizeof(*key)) == 0) {
+ /* If it's an optimized shader and its compilation has
+ * been started but isn't done, use the unoptimized
+ * shader so as not to cause a stall due to compilation.
+ */
+ if (iter->is_optimized &&
+ !util_queue_fence_is_signalled(&iter->optimized_ready)) {
+ memset(&key->opt, 0, sizeof(key->opt));
+ pipe_mutex_unlock(sel->mutex);
+ goto again;
+ }
+
+ if (iter->compilation_failed) {
+ pipe_mutex_unlock(sel->mutex);
+ return -1; /* skip the draw call */
+ }
+
state->current = iter;
pipe_mutex_unlock(sel->mutex);
return 0;
}
shader->selector = sel;
shader->key = *key;
+ shader->compiler_ctx_state = *compiler_state;
- r = si_shader_create(sctx->screen, sctx->tm, shader, &sctx->b.debug);
- if (unlikely(r)) {
- R600_ERR("Failed to build shader variant (type=%u) %d\n",
- sel->type, r);
- FREE(shader);
- pipe_mutex_unlock(sel->mutex);
- return r;
+ /* Compile the main shader part if it doesn't exist. This can happen
+ * if the initial guess was wrong. */
+ struct si_shader **mainp = si_get_main_shader_part(sel, key);
+ bool is_pure_monolithic =
+ sscreen->use_monolithic_shaders ||
+ memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
+
+ if (!*mainp && !is_pure_monolithic) {
+ struct si_shader *main_part = CALLOC_STRUCT(si_shader);
+
+ if (!main_part) {
+ FREE(shader);
+ pipe_mutex_unlock(sel->mutex);
+ return -ENOMEM; /* skip the draw call */
+ }
+
+ main_part->selector = sel;
+ main_part->key.as_es = key->as_es;
+ main_part->key.as_ls = key->as_ls;
+
+ if (si_compile_tgsi_shader(sscreen, compiler_state->tm,
+ main_part, false,
+ &compiler_state->debug) != 0) {
+ FREE(main_part);
+ FREE(shader);
+ pipe_mutex_unlock(sel->mutex);
+ return -ENOMEM; /* skip the draw call */
+ }
+ *mainp = main_part;
}
- si_shader_init_pm4_state(shader);
+
+ /* Monolithic-only shaders don't make a distinction between optimized
+ * and unoptimized. */
+ shader->is_monolithic =
+ is_pure_monolithic ||
+ memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
+
+ shader->is_optimized =
+ !is_pure_monolithic &&
+ memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
+ if (shader->is_optimized)
+ util_queue_fence_init(&shader->optimized_ready);
if (!sel->last_variant) {
sel->first_variant = shader;
sel->last_variant->next_variant = shader;
sel->last_variant = shader;
}
- state->current = shader;
+
+ /* If it's an optimized shader, compile it asynchronously. */
+ if (shader->is_optimized &&
+ !is_pure_monolithic &&
+ thread_index < 0) {
+ /* Compile it asynchronously. */
+ util_queue_add_job(&sscreen->shader_compiler_queue,
+ shader, &shader->optimized_ready,
+ si_build_shader_variant, NULL);
+
+ /* Use the default (unoptimized) shader for now. */
+ memset(&key->opt, 0, sizeof(key->opt));
+ pipe_mutex_unlock(sel->mutex);
+ goto again;
+ }
+
+ assert(!shader->is_optimized);
+ si_build_shader_variant(shader, thread_index);
+
+ if (!shader->compilation_failed)
+ state->current = shader;
+
pipe_mutex_unlock(sel->mutex);
- return 0;
+ return shader->compilation_failed ? -1 : 0;
}
static int si_shader_select(struct pipe_context *ctx,
- struct si_shader_ctx_state *state)
+ struct si_shader_ctx_state *state,
+ struct si_compiler_ctx_state *compiler_state)
{
- union si_shader_key key;
+ struct si_context *sctx = (struct si_context *)ctx;
+ struct si_shader_key key;
si_shader_selector_key(ctx, state->cso, &key);
- return si_shader_select_with_key(ctx, state, &key);
+ return si_shader_select_with_key(sctx->screen, state, compiler_state,
+ &key, -1);
}
static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
- union si_shader_key *key)
+ struct si_shader_key *key)
{
unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
case PIPE_SHADER_VERTEX:
switch (next_shader) {
case PIPE_SHADER_GEOMETRY:
- key->vs.as_es = 1;
+ key->as_es = 1;
break;
case PIPE_SHADER_TESS_CTRL:
case PIPE_SHADER_TESS_EVAL:
- key->vs.as_ls = 1;
+ key->as_ls = 1;
break;
+ default:
+ /* If POSITION isn't written, it can't be a HW VS.
+ * Assume that it's a HW LS. (the next shader is TCS)
+ * This heuristic is needed for separate shader objects.
+ */
+ if (!info->writes_position)
+ key->as_ls = 1;
}
break;
case PIPE_SHADER_TESS_EVAL:
- if (next_shader == PIPE_SHADER_GEOMETRY)
- key->tes.as_es = 1;
+ if (next_shader == PIPE_SHADER_GEOMETRY ||
+ !info->writes_position)
+ key->as_es = 1;
break;
}
}
+/**
+ * Compile the main shader part or the monolithic shader as part of
+ * si_shader_selector initialization. Since it can be done asynchronously,
+ * there is no way to report compile failures to applications.
+ */
+void si_init_shader_selector_async(void *job, int thread_index)
+{
+ struct si_shader_selector *sel = (struct si_shader_selector *)job;
+ struct si_screen *sscreen = sel->screen;
+ LLVMTargetMachineRef tm;
+ struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
+ unsigned i;
+
+ if (thread_index >= 0) {
+ assert(thread_index < ARRAY_SIZE(sscreen->tm));
+ tm = sscreen->tm[thread_index];
+ if (!debug->async)
+ debug = NULL;
+ } else {
+ tm = sel->compiler_ctx_state.tm;
+ }
+
+ /* Compile the main shader part for use with a prolog and/or epilog.
+ * If this fails, the driver will try to compile a monolithic shader
+ * on demand.
+ */
+ if (!sscreen->use_monolithic_shaders) {
+ struct si_shader *shader = CALLOC_STRUCT(si_shader);
+ void *tgsi_binary;
+
+ if (!shader) {
+ fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
+ return;
+ }
+
+ shader->selector = sel;
+ si_parse_next_shader_property(&sel->info, &shader->key);
+
+ tgsi_binary = si_get_tgsi_binary(sel);
+
+ /* Try to load the shader from the shader cache. */
+ mtx_lock(&sscreen->shader_cache_mutex);
+
+ if (tgsi_binary &&
+ si_shader_cache_load_shader(sscreen, tgsi_binary, shader)) {
+ pipe_mutex_unlock(sscreen->shader_cache_mutex);
+ } else {
+ pipe_mutex_unlock(sscreen->shader_cache_mutex);
+
+ /* Compile the shader if it hasn't been loaded from the cache. */
+ if (si_compile_tgsi_shader(sscreen, tm, shader, false,
+ debug) != 0) {
+ FREE(shader);
+ FREE(tgsi_binary);
+ fprintf(stderr, "radeonsi: can't compile a main shader part\n");
+ return;
+ }
+
+ if (tgsi_binary) {
+ mtx_lock(&sscreen->shader_cache_mutex);
+ if (!si_shader_cache_insert_shader(sscreen, tgsi_binary, shader, true))
+ FREE(tgsi_binary);
+ pipe_mutex_unlock(sscreen->shader_cache_mutex);
+ }
+ }
+
+ *si_get_main_shader_part(sel, &shader->key) = shader;
+
+ /* Unset "outputs_written" flags for outputs converted to
+ * DEFAULT_VAL, so that later inter-shader optimizations don't
+ * try to eliminate outputs that don't exist in the final
+ * shader.
+ *
+ * This is only done if non-monolithic shaders are enabled.
+ */
+ if ((sel->type == PIPE_SHADER_VERTEX ||
+ sel->type == PIPE_SHADER_TESS_EVAL) &&
+ !shader->key.as_ls &&
+ !shader->key.as_es) {
+ unsigned i;
+
+ for (i = 0; i < sel->info.num_outputs; i++) {
+ unsigned offset = shader->info.vs_output_param_offset[i];
+
+ if (offset <= EXP_PARAM_OFFSET_31)
+ continue;
+
+ unsigned name = sel->info.output_semantic_name[i];
+ unsigned index = sel->info.output_semantic_index[i];
+ unsigned id;
+
+ switch (name) {
+ case TGSI_SEMANTIC_GENERIC:
+ /* don't process indices the function can't handle */
+ if (index >= 60)
+ break;
+ /* fall through */
+ case TGSI_SEMANTIC_CLIPDIST:
+ id = si_shader_io_get_unique_index(name, index);
+ sel->outputs_written &= ~(1ull << id);
+ break;
+ case TGSI_SEMANTIC_POSITION: /* ignore these */
+ case TGSI_SEMANTIC_PSIZE:
+ case TGSI_SEMANTIC_CLIPVERTEX:
+ case TGSI_SEMANTIC_EDGEFLAG:
+ break;
+ default:
+ id = si_shader_io_get_unique_index2(name, index);
+ sel->outputs_written2 &= ~(1u << id);
+ }
+ }
+ }
+ }
+
+ /* Pre-compilation. */
+ if (sscreen->b.debug_flags & DBG_PRECOMPILE) {
+ struct si_shader_ctx_state state = {sel};
+ struct si_shader_key key;
+
+ memset(&key, 0, sizeof(key));
+ si_parse_next_shader_property(&sel->info, &key);
+
+ /* Set reasonable defaults, so that the shader key doesn't
+ * cause any code to be eliminated.
+ */
+ switch (sel->type) {
+ case PIPE_SHADER_TESS_CTRL:
+ key.part.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
+ break;
+ case PIPE_SHADER_FRAGMENT:
+ key.part.ps.prolog.bc_optimize_for_persp =
+ sel->info.uses_persp_center &&
+ sel->info.uses_persp_centroid;
+ key.part.ps.prolog.bc_optimize_for_linear =
+ sel->info.uses_linear_center &&
+ sel->info.uses_linear_centroid;
+ key.part.ps.epilog.alpha_func = PIPE_FUNC_ALWAYS;
+ for (i = 0; i < 8; i++)
+ if (sel->info.colors_written & (1 << i))
+ key.part.ps.epilog.spi_shader_col_format |=
+ V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
+ break;
+ }
+
+ if (si_shader_select_with_key(sscreen, &state,
+ &sel->compiler_ctx_state, &key,
+ thread_index))
+ fprintf(stderr, "radeonsi: can't create a monolithic shader\n");
+ }
+
+ /* The GS copy shader is always pre-compiled. */
+ if (sel->type == PIPE_SHADER_GEOMETRY) {
+ sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, tm, sel, debug);
+ if (!sel->gs_copy_shader) {
+ fprintf(stderr, "radeonsi: can't create GS copy shader\n");
+ return;
+ }
+
+ si_shader_vs(sscreen, sel->gs_copy_shader, sel);
+ }
+}
+
static void *si_create_shader_selector(struct pipe_context *ctx,
const struct pipe_shader_state *state)
{
if (!sel)
return NULL;
+ sel->screen = sscreen;
+ sel->compiler_ctx_state.tm = sctx->tm;
+ sel->compiler_ctx_state.debug = sctx->b.debug;
+ sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
sel->tokens = tgsi_dup_tokens(state->tokens);
if (!sel->tokens) {
FREE(sel);
u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
break;
- case PIPE_SHADER_VERTEX:
case PIPE_SHADER_TESS_CTRL:
+ /* Always reserve space for these. */
+ sel->patch_outputs_written |=
+ (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0)) |
+ (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0));
+ /* fall through */
+ case PIPE_SHADER_VERTEX:
case PIPE_SHADER_TESS_EVAL:
for (i = 0; i < sel->info.num_outputs; i++) {
unsigned name = sel->info.output_semantic_name[i];
sel->patch_outputs_written |=
1llu << si_shader_io_get_unique_index(name, index);
break;
- default:
+
+ case TGSI_SEMANTIC_GENERIC:
+ /* don't process indices the function can't handle */
+ if (index >= 60)
+ break;
+ /* fall through */
+ case TGSI_SEMANTIC_POSITION:
+ case TGSI_SEMANTIC_PSIZE:
+ case TGSI_SEMANTIC_CLIPDIST:
sel->outputs_written |=
1llu << si_shader_io_get_unique_index(name, index);
+ break;
+ case TGSI_SEMANTIC_CLIPVERTEX: /* ignore these */
+ case TGSI_SEMANTIC_EDGEFLAG:
+ break;
+ default:
+ sel->outputs_written2 |=
+ 1u << si_shader_io_get_unique_index2(name, index);
}
}
sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
break;
case PIPE_SHADER_FRAGMENT:
+ for (i = 0; i < sel->info.num_inputs; i++) {
+ unsigned name = sel->info.input_semantic_name[i];
+ unsigned index = sel->info.input_semantic_index[i];
+
+ switch (name) {
+ case TGSI_SEMANTIC_CLIPDIST:
+ case TGSI_SEMANTIC_GENERIC:
+ sel->inputs_read |=
+ 1llu << si_shader_io_get_unique_index(name, index);
+ break;
+ case TGSI_SEMANTIC_PCOORD: /* ignore this */
+ break;
+ default:
+ sel->inputs_read2 |=
+ 1u << si_shader_io_get_unique_index2(name, index);
+ }
+ }
+
for (i = 0; i < 8; i++)
if (sel->info.colors_written & (1 << i))
sel->colors_written_4bit |= 0xf << (4 * i);
break;
}
- if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL])
- sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1);
-
- if (sel->info.writes_memory)
- sel->db_shader_control |= S_02880C_EXEC_ON_HIER_FAIL(1) |
- S_02880C_EXEC_ON_NOOP(1);
-
- /* Compile the main shader part for use with a prolog and/or epilog. */
- if (sel->type != PIPE_SHADER_GEOMETRY &&
- !sscreen->use_monolithic_shaders) {
- struct si_shader *shader = CALLOC_STRUCT(si_shader);
- void *tgsi_binary;
-
- if (!shader)
- goto error;
-
- shader->selector = sel;
- si_parse_next_shader_property(&sel->info, &shader->key);
-
- tgsi_binary = si_get_tgsi_binary(sel);
-
- /* Try to load the shader from the shader cache. */
- pipe_mutex_lock(sscreen->shader_cache_mutex);
-
- if (tgsi_binary &&
- si_shader_cache_load_shader(sscreen, tgsi_binary, shader)) {
- FREE(tgsi_binary);
- } else {
- /* Compile the shader if it hasn't been loaded from the cache. */
- if (si_compile_tgsi_shader(sscreen, sctx->tm, shader, false,
- &sctx->b.debug) != 0) {
- FREE(shader);
- FREE(tgsi_binary);
- pipe_mutex_unlock(sscreen->shader_cache_mutex);
- goto error;
- }
-
- if (tgsi_binary &&
- !si_shader_cache_insert_shader(sscreen, tgsi_binary, shader))
- FREE(tgsi_binary);
- }
- pipe_mutex_unlock(sscreen->shader_cache_mutex);
-
- sel->main_shader_part = shader;
+ /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
+ *
+ * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
+ * --|-----------|------------|------------|--------------------|-------------------|-------------
+ * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
+ * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
+ * 2 | false | true | n/a | LateZ | 1 | 0
+ * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
+ * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
+ *
+ * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
+ * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
+ *
+ * Don't use ReZ without profiling !!!
+ *
+ * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
+ * shaders.
+ */
+ if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
+ /* Cases 3, 4. */
+ sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
+ S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
+ S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
+ } else if (sel->info.writes_memory) {
+ /* Case 2. */
+ sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
+ S_02880C_EXEC_ON_HIER_FAIL(1);
+ } else {
+ /* Case 1. */
+ sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
}
- /* Pre-compilation. */
- if (sel->type == PIPE_SHADER_GEOMETRY ||
- sscreen->b.debug_flags & DBG_PRECOMPILE) {
- struct si_shader_ctx_state state = {sel};
- union si_shader_key key;
+ (void) mtx_init(&sel->mutex, mtx_plain);
+ util_queue_fence_init(&sel->ready);
- memset(&key, 0, sizeof(key));
- si_parse_next_shader_property(&sel->info, &key);
-
- /* Set reasonable defaults, so that the shader key doesn't
- * cause any code to be eliminated.
- */
- switch (sel->type) {
- case PIPE_SHADER_TESS_CTRL:
- key.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
- break;
- case PIPE_SHADER_FRAGMENT:
- key.ps.epilog.alpha_func = PIPE_FUNC_ALWAYS;
- for (i = 0; i < 8; i++)
- if (sel->info.colors_written & (1 << i))
- key.ps.epilog.spi_shader_col_format |=
- V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
- break;
- }
-
- if (si_shader_select_with_key(ctx, &state, &key))
- goto error;
- }
+ if ((sctx->b.debug.debug_message && !sctx->b.debug.async) ||
+ sctx->is_debug ||
+ r600_can_dump_shader(&sscreen->b, sel->info.processor) ||
+ !util_queue_is_initialized(&sscreen->shader_compiler_queue))
+ si_init_shader_selector_async(sel, -1);
+ else
+ util_queue_add_job(&sscreen->shader_compiler_queue, sel,
+ &sel->ready, si_init_shader_selector_async,
+ NULL);
- pipe_mutex_init(sel->mutex);
return sel;
-
-error:
- fprintf(stderr, "radeonsi: can't create a shader\n");
- tgsi_free_tokens(sel->tokens);
- FREE(sel);
- return NULL;
}
static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
sctx->vs_shader.cso = sel;
sctx->vs_shader.current = sel ? sel->first_variant : NULL;
+ sctx->do_update_shaders = true;
si_mark_atom_dirty(sctx, &sctx->clip_regs);
r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
}
sctx->gs_shader.cso = sel;
sctx->gs_shader.current = sel ? sel->first_variant : NULL;
+ sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
+ sctx->do_update_shaders = true;
si_mark_atom_dirty(sctx, &sctx->clip_regs);
sctx->last_rast_prim = -1; /* reset this so that it gets updated */
r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
}
+static void si_update_tcs_tes_uses_prim_id(struct si_context *sctx)
+{
+ sctx->ia_multi_vgt_param_key.u.tcs_tes_uses_prim_id =
+ (sctx->tes_shader.cso &&
+ sctx->tes_shader.cso->info.uses_primid) ||
+ (sctx->tcs_shader.cso &&
+ sctx->tcs_shader.cso->info.uses_primid);
+}
+
static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
{
struct si_context *sctx = (struct si_context *)ctx;
sctx->tcs_shader.cso = sel;
sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
+ si_update_tcs_tes_uses_prim_id(sctx);
+ sctx->do_update_shaders = true;
if (enable_changed)
sctx->last_tcs = NULL; /* invalidate derived tess state */
sctx->tes_shader.cso = sel;
sctx->tes_shader.current = sel ? sel->first_variant : NULL;
+ sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
+ si_update_tcs_tes_uses_prim_id(sctx);
+ sctx->do_update_shaders = true;
si_mark_atom_dirty(sctx, &sctx->clip_regs);
sctx->last_rast_prim = -1; /* reset this so that it gets updated */
sctx->ps_shader.cso = sel;
sctx->ps_shader.current = sel ? sel->first_variant : NULL;
+ sctx->do_update_shaders = true;
si_mark_atom_dirty(sctx, &sctx->cb_render_state);
}
static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
{
+ if (shader->is_optimized) {
+ util_queue_fence_wait(&shader->optimized_ready);
+ util_queue_fence_destroy(&shader->optimized_ready);
+ }
+
if (shader->pm4) {
switch (shader->selector->type) {
case PIPE_SHADER_VERTEX:
- if (shader->key.vs.as_ls)
+ if (shader->key.as_ls)
si_pm4_delete_state(sctx, ls, shader->pm4);
- else if (shader->key.vs.as_es)
+ else if (shader->key.as_es)
si_pm4_delete_state(sctx, es, shader->pm4);
else
si_pm4_delete_state(sctx, vs, shader->pm4);
si_pm4_delete_state(sctx, hs, shader->pm4);
break;
case PIPE_SHADER_TESS_EVAL:
- if (shader->key.tes.as_es)
+ if (shader->key.as_es)
si_pm4_delete_state(sctx, es, shader->pm4);
else
si_pm4_delete_state(sctx, vs, shader->pm4);
break;
case PIPE_SHADER_GEOMETRY:
- si_pm4_delete_state(sctx, gs, shader->pm4);
- si_pm4_delete_state(sctx, vs, shader->gs_copy_shader->pm4);
+ if (shader->is_gs_copy_shader)
+ si_pm4_delete_state(sctx, vs, shader->pm4);
+ else
+ si_pm4_delete_state(sctx, gs, shader->pm4);
break;
case PIPE_SHADER_FRAGMENT:
si_pm4_delete_state(sctx, ps, shader->pm4);
[PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
};
+ util_queue_fence_wait(&sel->ready);
+
if (current_shader[sel->type]->cso == sel) {
current_shader[sel->type]->cso = NULL;
current_shader[sel->type]->current = NULL;
if (sel->main_shader_part)
si_delete_shader(sctx, sel->main_shader_part);
-
- pipe_mutex_destroy(sel->mutex);
+ if (sel->main_shader_part_ls)
+ si_delete_shader(sctx, sel->main_shader_part_ls);
+ if (sel->main_shader_part_es)
+ si_delete_shader(sctx, sel->main_shader_part_es);
+ if (sel->gs_copy_shader)
+ si_delete_shader(sctx, sel->gs_copy_shader);
+
+ util_queue_fence_destroy(&sel->ready);
+ mtx_destroy(&sel->mutex);
free(sel->tokens);
free(sel);
}
unsigned index, unsigned interpolate)
{
struct tgsi_shader_info *vsinfo = &vs->selector->info;
- unsigned j, ps_input_cntl = 0;
+ unsigned j, offset, ps_input_cntl = 0;
if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
(interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
for (j = 0; j < vsinfo->num_outputs; j++) {
if (name == vsinfo->output_semantic_name[j] &&
index == vsinfo->output_semantic_index[j]) {
- ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[j]);
+ offset = vs->info.vs_output_param_offset[j];
+
+ if (offset <= EXP_PARAM_OFFSET_31) {
+ /* The input is loaded from parameter memory. */
+ ps_input_cntl |= S_028644_OFFSET(offset);
+ } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
+ if (offset == EXP_PARAM_UNDEFINED) {
+ /* This can happen with depth-only rendering. */
+ offset = 0;
+ } else {
+ /* The input is a DEFAULT_VAL constant. */
+ assert(offset >= EXP_PARAM_DEFAULT_VAL_0000 &&
+ offset <= EXP_PARAM_DEFAULT_VAL_1111);
+ offset -= EXP_PARAM_DEFAULT_VAL_0000;
+ }
+
+ ps_input_cntl = S_028644_OFFSET(0x20) |
+ S_028644_DEFAULT_VAL(offset);
+ }
break;
}
}
}
}
- if (ps->key.ps.prolog.color_two_side) {
+ if (ps->key.part.ps.prolog.color_two_side) {
unsigned bcol = TGSI_SEMANTIC_BCOLOR;
for (i = 0; i < 2; i++) {
if (sctx->init_config_has_vgt_flush)
return;
+ /* Done by Vulkan before VGT_FLUSH. */
+ si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
+ si_pm4_cmd_add(sctx->init_config,
+ EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
+ si_pm4_cmd_end(sctx->init_config, false);
+
/* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
es->esgs_itemsize * gs->gs_input_verts_per_prim;
unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
- gs->max_gsvs_emit_size * (gs->max_gs_stream + 1);
+ gs->max_gsvs_emit_size;
min_esgs_ring_size = align(min_esgs_ring_size, alignment);
esgs_ring_size = align(esgs_ring_size, alignment);
if (update_esgs) {
pipe_resource_reference(&sctx->esgs_ring, NULL);
- sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
- PIPE_USAGE_DEFAULT,
- esgs_ring_size);
+ sctx->esgs_ring =
+ r600_aligned_buffer_create(sctx->b.b.screen,
+ R600_RESOURCE_FLAG_UNMAPPABLE,
+ PIPE_USAGE_DEFAULT,
+ esgs_ring_size, alignment);
if (!sctx->esgs_ring)
return false;
}
if (update_gsvs) {
pipe_resource_reference(&sctx->gsvs_ring, NULL);
- sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
- PIPE_USAGE_DEFAULT,
- gsvs_ring_size);
+ sctx->gsvs_ring =
+ r600_aligned_buffer_create(sctx->b.b.screen,
+ R600_RESOURCE_FLAG_UNMAPPABLE,
+ PIPE_USAGE_DEFAULT,
+ gsvs_ring_size, alignment);
if (!sctx->gsvs_ring)
return false;
}
sctx->esgs_ring, 0, sctx->esgs_ring->width0,
false, false, 0, 0, 0);
}
- if (sctx->gsvs_ring)
- si_set_ring_buffer(&sctx->b.b, SI_VS_RING_GSVS,
+ if (sctx->gsvs_ring) {
+ si_set_ring_buffer(&sctx->b.b, SI_RING_GSVS,
sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
false, false, 0, 0, 0);
- return true;
-}
-
-static void si_update_gsvs_ring_bindings(struct si_context *sctx)
-{
- unsigned gsvs_itemsize = sctx->gs_shader.cso->max_gsvs_emit_size;
- uint64_t offset;
-
- if (!sctx->gsvs_ring || gsvs_itemsize == sctx->last_gsvs_itemsize)
- return;
-
- sctx->last_gsvs_itemsize = gsvs_itemsize;
-
- si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS0,
- sctx->gsvs_ring, gsvs_itemsize,
- 64, true, true, 4, 16, 0);
-
- offset = gsvs_itemsize * 64;
- si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS1,
- sctx->gsvs_ring, gsvs_itemsize,
- 64, true, true, 4, 16, offset);
-
- offset = (gsvs_itemsize * 2) * 64;
- si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS2,
- sctx->gsvs_ring, gsvs_itemsize,
- 64, true, true, 4, 16, offset);
+ }
- offset = (gsvs_itemsize * 3) * 64;
- si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS3,
- sctx->gsvs_ring, gsvs_itemsize,
- 64, true, true, 4, 16, offset);
+ return true;
}
/**
return r;
/* Update the shader state to use the new shader bo. */
- si_shader_init_pm4_state(shader);
+ si_shader_init_pm4_state(sctx->screen, shader);
r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
if (scratch_needed_size > 0) {
if (scratch_needed_size > current_scratch_buffer_size) {
/* Create a bigger scratch buffer */
- pipe_resource_reference(
- (struct pipe_resource**)&sctx->scratch_buffer,
- NULL);
+ r600_resource_reference(&sctx->scratch_buffer, NULL);
- sctx->scratch_buffer =
- si_resource_create_custom(&sctx->screen->b.b,
- PIPE_USAGE_DEFAULT, scratch_needed_size);
+ sctx->scratch_buffer = (struct r600_resource*)
+ r600_aligned_buffer_create(&sctx->screen->b.b,
+ R600_RESOURCE_FLAG_UNMAPPABLE,
+ PIPE_USAGE_DEFAULT,
+ scratch_needed_size, 256);
if (!sctx->scratch_buffer)
return false;
- sctx->emit_scratch_reloc = true;
+
+ si_mark_atom_dirty(sctx, &sctx->scratch_state);
+ r600_context_add_resource_size(&sctx->b.b,
+ &sctx->scratch_buffer->b.b);
}
/* Update the shaders, so they are using the latest scratch. The
S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
if (spi_tmpring_size != sctx->spi_tmpring_size) {
sctx->spi_tmpring_size = spi_tmpring_size;
- sctx->emit_scratch_reloc = true;
+ si_mark_atom_dirty(sctx, &sctx->scratch_state);
}
return true;
}
static void si_init_tess_factor_ring(struct si_context *sctx)
{
- unsigned offchip_blocks = sctx->b.chip_class >= CIK ? 256 : 64;
- assert(!sctx->tf_ring);
+ bool double_offchip_buffers = sctx->b.chip_class >= CIK &&
+ sctx->b.family != CHIP_CARRIZO &&
+ sctx->b.family != CHIP_STONEY;
+ unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
+ unsigned max_offchip_buffers = max_offchip_buffers_per_se *
+ sctx->screen->b.info.max_se;
+ unsigned offchip_granularity;
+
+ switch (sctx->screen->tess_offchip_block_dw_size) {
+ default:
+ assert(0);
+ /* fall through */
+ case 8192:
+ offchip_granularity = V_03093C_X_8K_DWORDS;
+ break;
+ case 4096:
+ offchip_granularity = V_03093C_X_4K_DWORDS;
+ break;
+ }
- sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
- PIPE_USAGE_DEFAULT,
- 32768 * sctx->screen->b.info.max_se);
+ switch (sctx->b.chip_class) {
+ case SI:
+ max_offchip_buffers = MIN2(max_offchip_buffers, 126);
+ break;
+ case CIK:
+ max_offchip_buffers = MIN2(max_offchip_buffers, 508);
+ break;
+ case VI:
+ default:
+ max_offchip_buffers = MIN2(max_offchip_buffers, 512);
+ break;
+ }
+
+ assert(!sctx->tf_ring);
+ sctx->tf_ring = r600_aligned_buffer_create(sctx->b.b.screen,
+ R600_RESOURCE_FLAG_UNMAPPABLE,
+ PIPE_USAGE_DEFAULT,
+ 32768 * sctx->screen->b.info.max_se,
+ 256);
if (!sctx->tf_ring)
return;
assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
- sctx->tess_offchip_ring = pipe_buffer_create(sctx->b.b.screen,
- PIPE_BIND_CUSTOM,
- PIPE_USAGE_DEFAULT,
- offchip_blocks *
- SI_TESS_OFFCHIP_BLOCK_SIZE);
+ sctx->tess_offchip_ring =
+ r600_aligned_buffer_create(sctx->b.b.screen,
+ R600_RESOURCE_FLAG_UNMAPPABLE,
+ PIPE_USAGE_DEFAULT,
+ max_offchip_buffers *
+ sctx->screen->tess_offchip_block_dw_size * 4,
+ 256);
if (!sctx->tess_offchip_ring)
return;
/* Append these registers to the init config state. */
if (sctx->b.chip_class >= CIK) {
+ if (sctx->b.chip_class >= VI)
+ --max_offchip_buffers;
+
si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
S_030938_SIZE(sctx->tf_ring->width0 / 4));
si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
r600_resource(sctx->tf_ring)->gpu_address >> 8);
si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
- S_03093C_OFFCHIP_BUFFERING(offchip_blocks - 1) |
- S_03093C_OFFCHIP_GRANULARITY(V_03093C_X_8K_DWORDS));
+ S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
+ S_03093C_OFFCHIP_GRANULARITY(offchip_granularity));
} else {
+ assert(offchip_granularity == V_03093C_X_8K_DWORDS);
si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
S_008988_SIZE(sctx->tf_ring->width0 / 4));
si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
r600_resource(sctx->tf_ring)->gpu_address >> 8);
si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
- S_0089B0_OFFCHIP_BUFFERING(offchip_blocks - 1));
+ S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers));
}
/* Flush the context to re-emit the init_config state.
if (sctx->tes_shader.cso) {
stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
- S_028B54_HS_EN(1);
+ S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
if (sctx->gs_shader.cso)
stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
bool si_update_shaders(struct si_context *sctx)
{
struct pipe_context *ctx = (struct pipe_context*)sctx;
+ struct si_compiler_ctx_state compiler_state;
struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
+ struct si_shader *old_vs = si_get_vs_state(sctx);
+ bool old_clip_disable = old_vs ? old_vs->key.opt.hw_vs.clip_disable : false;
int r;
+ compiler_state.tm = sctx->tm;
+ compiler_state.debug = sctx->b.debug;
+ compiler_state.is_debug_context = sctx->is_debug;
+
/* Update stages before GS. */
if (sctx->tes_shader.cso) {
if (!sctx->tf_ring) {
}
/* VS as LS */
- r = si_shader_select(ctx, &sctx->vs_shader);
+ r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
if (r)
return false;
si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
if (sctx->tcs_shader.cso) {
- r = si_shader_select(ctx, &sctx->tcs_shader);
+ r = si_shader_select(ctx, &sctx->tcs_shader,
+ &compiler_state);
if (r)
return false;
si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
return false;
}
- r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader);
+ r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
+ &compiler_state);
if (r)
return false;
si_pm4_bind_state(sctx, hs,
sctx->fixed_func_tcs_shader.current->pm4);
}
- r = si_shader_select(ctx, &sctx->tes_shader);
+ r = si_shader_select(ctx, &sctx->tes_shader, &compiler_state);
if (r)
return false;
}
} else if (sctx->gs_shader.cso) {
/* VS as ES */
- r = si_shader_select(ctx, &sctx->vs_shader);
+ r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
if (r)
return false;
si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
+
+ si_pm4_bind_state(sctx, ls, NULL);
+ si_pm4_bind_state(sctx, hs, NULL);
} else {
/* VS as VS */
- r = si_shader_select(ctx, &sctx->vs_shader);
+ r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
if (r)
return false;
si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
si_update_so(sctx, sctx->vs_shader.cso);
+
+ si_pm4_bind_state(sctx, ls, NULL);
+ si_pm4_bind_state(sctx, hs, NULL);
}
/* Update GS. */
if (sctx->gs_shader.cso) {
- r = si_shader_select(ctx, &sctx->gs_shader);
+ r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state);
if (r)
return false;
si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
- si_pm4_bind_state(sctx, vs, sctx->gs_shader.current->gs_copy_shader->pm4);
+ si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
si_update_so(sctx, sctx->gs_shader.cso);
if (!si_update_gs_ring_buffers(sctx))
return false;
-
- si_update_gsvs_ring_bindings(sctx);
} else {
si_pm4_bind_state(sctx, gs, NULL);
si_pm4_bind_state(sctx, es, NULL);
si_update_vgt_shader_config(sctx);
+ if (old_clip_disable != si_get_vs_state(sctx)->key.opt.hw_vs.clip_disable)
+ si_mark_atom_dirty(sctx, &sctx->clip_regs);
+
if (sctx->ps_shader.cso) {
unsigned db_shader_control;
- r = si_shader_select(ctx, &sctx->ps_shader);
+ r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state);
if (r)
return false;
si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
db_shader_control =
sctx->ps_shader.cso->db_shader_control |
- S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS) |
- S_02880C_Z_ORDER(sctx->ps_shader.current->z_order);
+ S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
sctx->sprite_coord_enable != rs->sprite_coord_enable ||
si_mark_atom_dirty(sctx, &sctx->db_render_state);
}
- if (sctx->smoothing_enabled != sctx->ps_shader.current->key.ps.epilog.poly_line_smoothing) {
- sctx->smoothing_enabled = sctx->ps_shader.current->key.ps.epilog.poly_line_smoothing;
+ if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
+ sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
si_mark_atom_dirty(sctx, &sctx->msaa_config);
if (sctx->b.chip_class == SI)
si_mark_atom_dirty(sctx, &sctx->db_render_state);
+
+ if (sctx->framebuffer.nr_samples <= 1)
+ si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
}
}
if (!si_update_spi_tmpring_size(sctx))
return false;
}
+
+ if (sctx->b.chip_class >= CIK)
+ si_mark_atom_dirty(sctx, &sctx->prefetch_L2);
+
+ sctx->do_update_shaders = false;
return true;
}
+static void si_emit_scratch_state(struct si_context *sctx,
+ struct r600_atom *atom)
+{
+ struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
+
+ radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
+ sctx->spi_tmpring_size);
+
+ if (sctx->scratch_buffer) {
+ radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
+ sctx->scratch_buffer, RADEON_USAGE_READWRITE,
+ RADEON_PRIO_SCRATCH_BUFFER);
+ }
+}
+
void si_init_shader_functions(struct si_context *sctx)
{
si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
+ si_init_atom(sctx, &sctx->scratch_state, &sctx->atoms.s.scratch_state,
+ si_emit_scratch_state);
sctx->b.b.create_vs_state = si_create_shader_selector;
sctx->b.b.create_tcs_state = si_create_shader_selector;
projects / mesa.git / blobdiff