struct si_pm4_state *pm4)
{
const struct si_shader_info *info = &tes->info;
- unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
- unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
- bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
- bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
+ unsigned tes_prim_mode = info->base.tess.primitive_mode;
+ unsigned tes_spacing = info->base.tess.spacing;
+ bool tes_vertex_order_cw = !info->base.tess.ccw;
+ bool tes_point_mode = info->base.tess.point_mode;
unsigned type, partitioning, topology, distribution_mode;
switch (tes_prim_mode) {
- case PIPE_PRIM_LINES:
+ case GL_LINES:
type = V_028B6C_TESS_ISOLINE;
break;
- case PIPE_PRIM_TRIANGLES:
+ case GL_TRIANGLES:
type = V_028B6C_TESS_TRIANGLE;
break;
- case PIPE_PRIM_QUADS:
+ case GL_QUADS:
type = V_028B6C_TESS_QUAD;
break;
default:
}
switch (tes_spacing) {
- case PIPE_TESS_SPACING_FRACTIONAL_ODD:
+ case TESS_SPACING_FRACTIONAL_ODD:
partitioning = V_028B6C_PART_FRAC_ODD;
break;
- case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
+ case TESS_SPACING_FRACTIONAL_EVEN:
partitioning = V_028B6C_PART_FRAC_EVEN;
break;
- case PIPE_TESS_SPACING_EQUAL:
+ case TESS_SPACING_EQUAL:
partitioning = V_028B6C_PART_INTEGER;
break;
default:
if (tes_point_mode)
topology = V_028B6C_OUTPUT_POINT;
- else if (tes_prim_mode == PIPE_PRIM_LINES)
+ else if (tes_prim_mode == GL_LINES)
topology = V_028B6C_OUTPUT_LINE;
else if (tes_vertex_order_cw)
/* for some reason, this must be the other way around */
unsigned vtx_reuse_depth = 30;
if (sel->info.stage == MESA_SHADER_TESS_EVAL &&
- sel->info.properties[TGSI_PROPERTY_TES_SPACING] == PIPE_TESS_SPACING_FRACTIONAL_ODD)
+ sel->info.base.tess.spacing == TESS_SPACING_FRACTIONAL_ODD)
vtx_reuse_depth = 14;
assert(pm4->shader);
return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
if (gs->info.stage == MESA_SHADER_TESS_EVAL) {
- if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
+ if (gs->info.base.tess.point_mode)
return PIPE_PRIM_POINTS;
- if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
+ if (gs->info.base.tess.primitive_mode == GL_LINES)
return PIPE_PRIM_LINES;
return PIPE_PRIM_TRIANGLES;
}
unsigned num_user_sgprs;
unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
uint64_t va;
- unsigned window_space = gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
+ bool window_space = gs_info->stage == MESA_SHADER_VERTEX ?
+ gs_info->base.vs.window_space_position : 0;
bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
unsigned input_prim = si_get_input_prim(gs_sel);
if (es_stage == MESA_SHADER_VERTEX) {
es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
- if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
+ if (es_info->base.vs.blit_sgprs_amd) {
num_user_sgprs =
- SI_SGPR_VS_BLIT_DATA + es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
+ SI_SGPR_VS_BLIT_DATA + es_info->base.vs.blit_sgprs_amd;
} else {
num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
}
unsigned num_user_sgprs, vgpr_comp_cnt;
uint64_t va;
unsigned nparams, oc_lds_en;
- unsigned window_space = info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
+ bool window_space = info->stage == MESA_SHADER_VERTEX ?
+ info->base.vs.window_space_position : 0;
bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
pm4 = si_get_shader_pm4_state(shader);
} else if (shader->selector->info.stage == MESA_SHADER_VERTEX) {
vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, enable_prim_id);
- if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
- num_user_sgprs = SI_SGPR_VS_BLIT_DATA + info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
+ if (info->base.vs.blit_sgprs_amd) {
+ num_user_sgprs = SI_SGPR_VS_BLIT_DATA + info->base.vs.blit_sgprs_amd;
} else {
num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
}
void si_shader_selector_key_vs(struct si_context *sctx, struct si_shader_selector *vs,
struct si_shader_key *key, struct si_vs_prolog_bits *prolog_key)
{
- if (!sctx->vertex_elements || vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD])
+ if (!sctx->vertex_elements || vs->info.base.vs.blit_sgprs_amd)
return;
struct si_vertex_elements *elts = sctx->vertex_elements;
}
key->part.tcs.epilog.prim_mode =
- sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
+ sctx->tes_shader.cso->info.base.tess.primitive_mode;
key->part.tcs.epilog.invoc0_tess_factors_are_def =
sel->info.tessfactors_are_def_in_all_invocs;
key->part.tcs.epilog.tes_reads_tess_factors = sctx->tes_shader.cso->info.reads_tess_factors;
static void si_parse_next_shader_property(const struct si_shader_info *info, bool streamout,
struct si_shader_key *key)
{
- unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
+ gl_shader_stage next_shader = info->base.next_stage;
switch (info->stage) {
case MESA_SHADER_VERTEX:
switch (next_shader) {
- case PIPE_SHADER_GEOMETRY:
+ case MESA_SHADER_GEOMETRY:
key->as_es = 1;
break;
- case PIPE_SHADER_TESS_CTRL:
- case PIPE_SHADER_TESS_EVAL:
+ case MESA_SHADER_TESS_CTRL:
+ case MESA_SHADER_TESS_EVAL:
key->as_ls = 1;
break;
default:
break;
case MESA_SHADER_TESS_EVAL:
- if (next_shader == PIPE_SHADER_GEOMETRY || !info->writes_position)
+ if (next_shader == MESA_SHADER_GEOMETRY || !info->writes_position)
key->as_es = 1;
break;
}
sel->num_vs_inputs =
- sel->info.stage == MESA_SHADER_VERTEX && !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]
+ sel->info.stage == MESA_SHADER_VERTEX && !sel->info.base.vs.blit_sgprs_amd
? sel->info.num_inputs
: 0;
sel->num_vbos_in_user_sgprs = MIN2(sel->num_vs_inputs, sscreen->num_vbos_in_user_sgprs);
/* The prolog is a no-op if there are no inputs. */
sel->vs_needs_prolog = sel->info.stage == MESA_SHADER_VERTEX && sel->info.num_inputs &&
- !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
+ !sel->info.base.vs.blit_sgprs_amd;
sel->prim_discard_cs_allowed =
sel->info.stage == MESA_SHADER_VERTEX && !sel->info.uses_bindless_images &&
!sel->info.uses_bindless_samplers && !sel->info.writes_memory &&
!sel->info.writes_viewport_index &&
- !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] && !sel->so.num_outputs;
+ !sel->info.base.vs.window_space_position && !sel->so.num_outputs;
switch (sel->info.stage) {
case MESA_SHADER_GEOMETRY:
assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
/* Only for TES: */
- if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
- sel->rast_prim = PIPE_PRIM_POINTS;
- else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
- sel->rast_prim = PIPE_PRIM_LINE_STRIP;
- else
+ if (sel->info.stage == MESA_SHADER_TESS_EVAL) {
+ if (sel->info.base.tess.point_mode)
+ sel->rast_prim = PIPE_PRIM_POINTS;
+ else if (sel->info.base.tess.primitive_mode == GL_LINES)
+ sel->rast_prim = PIPE_PRIM_LINE_STRIP;
+ else
+ sel->rast_prim = PIPE_PRIM_TRIANGLES;
+ } else {
sel->rast_prim = PIPE_PRIM_TRIANGLES;
+ }
break;
case MESA_SHADER_FRAGMENT:
sel->info.writes_position &&
!sel->info.writes_viewport_index && /* cull only against viewport 0 */
!sel->info.writes_memory && !sel->so.num_outputs &&
- !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] &&
- !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
+ (sel->info.stage != MESA_SHADER_VERTEX ||
+ (!sel->info.base.vs.blit_sgprs_amd &&
+ !sel->info.base.vs.window_space_position));
/* PA_CL_VS_OUT_CNTL */
if (sctx->chip_class <= GFX9)
{
if (next_hw_vs &&
(!old_hw_vs ||
- old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
- next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
+ (old_hw_vs->info.stage == MESA_SHADER_VERTEX && old_hw_vs->info.base.vs.window_space_position) !=
+ (next_hw_vs->info.stage == MESA_SHADER_VERTEX && next_hw_vs->info.base.vs.window_space_position) ||
old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
old_hw_vs->culldist_mask != next_hw_vs->culldist_mask || !old_hw_vs_variant ||
sctx->vs_shader.cso = sel;
sctx->vs_shader.current = sel ? sel->first_variant : NULL;
- sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] : 0;
+ sctx->num_vs_blit_sgprs = sel ? sel->info.base.vs.blit_sgprs_amd : 0;
if (si_update_ngg(sctx))
si_shader_change_notify(sctx);
unsigned semantic, enum glsl_interp_mode interpolate)
{
struct si_shader_info *vsinfo = &vs->selector->info;
- unsigned j, offset, ps_input_cntl = 0;
+ unsigned offset, ps_input_cntl = 0;
if (interpolate == INTERP_MODE_FLAT ||
(interpolate == INTERP_MODE_COLOR && sctx->flatshade) ||
ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
}
- /* TODO: This search can be removed if we add a lookup table from semantic to index. */
- for (j = 0; j < vsinfo->num_outputs; j++) {
- if (semantic == vsinfo->output_semantic[j]) {
- offset = vs->info.vs_output_param_offset[j];
-
- if (offset <= AC_EXP_PARAM_OFFSET_31) {
- /* The input is loaded from parameter memory. */
- ps_input_cntl |= S_028644_OFFSET(offset);
- } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
- if (offset == AC_EXP_PARAM_UNDEFINED) {
- /* This can happen with depth-only rendering. */
- offset = 0;
- } else {
- /* The input is a DEFAULT_VAL constant. */
- assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
- offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
- offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
- }
+ int vs_slot = vsinfo->output_semantic_to_slot[semantic];
+ if (vs_slot >= 0) {
+ offset = vs->info.vs_output_param_offset[vs_slot];
- ps_input_cntl = S_028644_OFFSET(0x20) | S_028644_DEFAULT_VAL(offset);
+ if (offset <= AC_EXP_PARAM_OFFSET_31) {
+ /* The input is loaded from parameter memory. */
+ ps_input_cntl |= S_028644_OFFSET(offset);
+ } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
+ if (offset == AC_EXP_PARAM_UNDEFINED) {
+ /* This can happen with depth-only rendering. */
+ offset = 0;
+ } else {
+ /* The input is a DEFAULT_VAL constant. */
+ assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
+ offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
+ offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
}
- break;
+
+ ps_input_cntl = S_028644_OFFSET(0x20) | S_028644_DEFAULT_VAL(offset);
+ }
+ } else {
+ /* VS output not found. */
+ if (semantic == VARYING_SLOT_PRIMITIVE_ID) {
+ /* PrimID is written after the last output when HW VS is used. */
+ ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
+ } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
+ /* No corresponding output found, load defaults into input.
+ * Don't set any other bits.
+ * (FLAT_SHADE=1 completely changes behavior) */
+ ps_input_cntl = S_028644_OFFSET(0x20);
+ /* D3D 9 behaviour. GL is undefined */
+ if (semantic == VARYING_SLOT_COL0)
+ ps_input_cntl |= S_028644_DEFAULT_VAL(3);
}
}
- if (j == vsinfo->num_outputs && semantic == VARYING_SLOT_PRIMITIVE_ID)
- /* PrimID is written after the last output when HW VS is used. */
- ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
- else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
- /* No corresponding output found, load defaults into input.
- * Don't set any other bits.
- * (FLAT_SHADE=1 completely changes behavior) */
- ps_input_cntl = S_028644_OFFSET(0x20);
- /* D3D 9 behaviour. GL is undefined */
- if (semantic == VARYING_SLOT_COL0)
- ps_input_cntl |= S_028644_DEFAULT_VAL(3);
- }
return ps_input_cntl;
}
projects / mesa.git / blobdiff