#include "sid.h"
#include "compiler/nir/nir_serialize.h"
+#include "nir/tgsi_to_nir.h"
#include "tgsi/tgsi_parse.h"
#include "util/hash_table.h"
#include "util/crc32.h"
}
si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
- S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
+ S_00B428_VGPRS((shader->config.num_vgprs - 1) /
+ (sscreen->ge_wave_size == 32 ? 8 : 4)) |
(sscreen->info.chip_class <= GFX9 ?
S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
S_00B428_DX10_CLAMP(1) |
S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
+ S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
S_00B428_FLOAT_MODE(shader->config.float_mode) |
S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
S_00B228_DX10_CLAMP(1) |
S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
+ S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
S_00B228_FLOAT_MODE(shader->config.float_mode) |
S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
uint32_t rsrc2 =
radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
- radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
- SI_TRACKED_VGT_REUSE_OFF,
- shader->ctx_reg.ngg.vgt_reuse_off);
radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
SI_TRACKED_SPI_VS_OUT_CONFIG,
shader->ctx_reg.ngg.spi_vs_out_config);
if (initial_cdw != sctx->gfx_cs->current.cdw)
sctx->context_roll = true;
-
- if (shader->ge_cntl != sctx->last_multi_vgt_param) {
- radeon_set_uconfig_reg(sctx->gfx_cs, R_03096C_GE_CNTL, shader->ge_cntl);
- sctx->last_multi_vgt_param = shader->ge_cntl;
- }
}
static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
}
-static void si_set_ge_pc_alloc(struct si_screen *sscreen,
- struct si_pm4_state *pm4, bool culling)
-{
- si_pm4_set_reg(pm4, R_030980_GE_PC_ALLOC,
- S_030980_OVERSUB_EN(1) |
- S_030980_NUM_PC_LINES((culling ? 256 : 128) * sscreen->info.max_se - 1));
-}
-
unsigned si_get_input_prim(const struct si_shader_selector *gs)
{
if (gs->type == PIPE_SHADER_GEOMETRY)
}
/* TODO: Set this correctly if the primitive type is set in the shader key. */
- return PIPE_PRIM_TRIANGLES;
+ return PIPE_PRIM_TRIANGLES; /* worst case for all callers */
}
/**
si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
- S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
+ S_00B228_VGPRS((shader->config.num_vgprs - 1) /
+ (sscreen->ge_wave_size == 32 ? 8 : 4)) |
S_00B228_FLOAT_MODE(shader->config.float_mode) |
S_00B228_DX10_CLAMP(1) |
S_00B228_MEM_ORDERED(1) |
+ S_00B228_WGP_MODE(1) |
S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
S_00B22C_LDS_SIZE(shader->config.lds_size));
- si_set_ge_pc_alloc(sscreen, pm4, false);
nparams = MAX2(shader->info.nr_param_exports, 1);
shader->ctx_reg.ngg.spi_vs_out_config =
S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
shader->ngg.max_vert_out_per_gs_instance);
- /* User edge flags are set by the pos exports. If user edge flags are
- * not used, we must use hw-generated edge flags and pass them via
- * the prim export to prevent drawing lines on internal edges of
- * decomposed primitives (such as quads) with polygon mode = lines.
- *
- * TODO: We should combine hw-generated edge flags with user edge
- * flags in the shader.
+ /* Always output hw-generated edge flags and pass them via the prim
+ * export to prevent drawing lines on internal edges of decomposed
+ * primitives (such as quads) with polygon mode = lines. Only VS needs
+ * this.
*/
shader->ctx_reg.ngg.pa_cl_ngg_cntl =
- S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX &&
- !gs_info->writes_edgeflag);
+ S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX);
shader->ge_cntl =
S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts) |
S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
+ /* Bug workaround for a possible hang with non-tessellation cases.
+ * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
+ *
+ * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
+ */
+ if ((sscreen->info.family == CHIP_NAVI10 ||
+ sscreen->info.family == CHIP_NAVI12 ||
+ sscreen->info.family == CHIP_NAVI14) &&
+ (es_type == PIPE_SHADER_VERTEX || gs_type == PIPE_SHADER_VERTEX) && /* = no tess */
+ shader->ngg.hw_max_esverts != 256) {
+ shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
+
+ if (shader->ngg.hw_max_esverts > 5) {
+ shader->ge_cntl |=
+ S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
+ }
+ }
+
if (window_space) {
shader->ctx_reg.ngg.pa_cl_vte_cntl =
S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
}
-
- shader->ctx_reg.ngg.vgt_reuse_off =
- S_028AB4_REUSE_OFF(sscreen->info.family == CHIP_NAVI10 &&
- sscreen->info.chip_external_rev == 0x1 &&
- es_type == PIPE_SHADER_TESS_EVAL);
}
static void si_emit_shader_vs(struct si_context *sctx)
vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
} else if (shader->selector->type == PIPE_SHADER_VERTEX) {
- /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
- * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
- * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
- */
- vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
+ if (sscreen->info.chip_class >= GFX10) {
+ vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
+ } else {
+ /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
+ * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
+ * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
+ */
+ vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
+ }
if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
- if (sscreen->info.chip_class >= GFX10)
- si_set_ge_pc_alloc(sscreen, pm4, false);
- uint32_t rsrc1 = S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
+ uint32_t rsrc1 = S_00B128_VGPRS((shader->config.num_vgprs - 1) /
+ (sscreen->ge_wave_size == 32 ? 8 : 4)) |
S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
S_00B128_DX10_CLAMP(1) |
S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
/* Set interpolation controls. */
- spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
+ spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
+ S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32);
shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
uint32_t rsrc1 =
- S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
+ S_00B028_VGPRS((shader->config.num_vgprs - 1) /
+ (sscreen->ps_wave_size == 32 ? 8 : 4)) |
S_00B028_DX10_CLAMP(1) |
S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
S_00B028_FLOAT_MODE(shader->config.float_mode);
static unsigned si_get_alpha_test_func(struct si_context *sctx)
{
/* Alpha-test should be disabled if colorbuffer 0 is integer. */
- if (sctx->queued.named.dsa)
- return sctx->queued.named.dsa->alpha_func;
-
- return PIPE_FUNC_ALWAYS;
+ return sctx->queued.named.dsa->alpha_func;
}
void si_shader_selector_key_vs(struct si_context *sctx,
/* Find out if PS is disabled. */
bool ps_disabled = true;
if (ps) {
- const struct si_state_blend *blend = sctx->queued.named.blend;
- bool alpha_to_coverage = blend && blend->alpha_to_coverage;
bool ps_modifies_zs = ps->info.uses_kill ||
ps->info.writes_z ||
ps->info.writes_stencil ||
ps->info.writes_samplemask ||
- alpha_to_coverage ||
+ sctx->queued.named.blend->alpha_to_coverage ||
si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
unsigned ps_colormask = si_get_total_colormask(sctx);
key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
break;
case PIPE_SHADER_TESS_EVAL:
+ key->as_ngg = stages_key.u.ngg;
+
if (sctx->gs_shader.cso)
key->as_es = 1;
else {
- key->as_ngg = stages_key.u.ngg;
si_shader_selector_key_hw_vs(sctx, sel, key);
if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
sel->info.colors_written == 0x1)
key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
- if (blend) {
- /* Select the shader color format based on whether
- * blending or alpha are needed.
- */
- key->part.ps.epilog.spi_shader_col_format =
- (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
- sctx->framebuffer.spi_shader_col_format_blend_alpha) |
- (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
- sctx->framebuffer.spi_shader_col_format_blend) |
- (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
- sctx->framebuffer.spi_shader_col_format_alpha) |
- (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
- sctx->framebuffer.spi_shader_col_format);
- key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
-
- /* The output for dual source blending should have
- * the same format as the first output.
- */
- if (blend->dual_src_blend)
- key->part.ps.epilog.spi_shader_col_format |=
- (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
- } else
- key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
+ /* Select the shader color format based on whether
+ * blending or alpha are needed.
+ */
+ key->part.ps.epilog.spi_shader_col_format =
+ (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
+ sctx->framebuffer.spi_shader_col_format_blend_alpha) |
+ (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
+ sctx->framebuffer.spi_shader_col_format_blend) |
+ (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
+ sctx->framebuffer.spi_shader_col_format_alpha) |
+ (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
+ sctx->framebuffer.spi_shader_col_format);
+ key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
+
+ /* The output for dual source blending should have
+ * the same format as the first output.
+ */
+ if (blend->dual_src_blend) {
+ key->part.ps.epilog.spi_shader_col_format |=
+ (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
+ }
/* If alpha-to-coverage is enabled, we have to export alpha
* even if there is no color buffer.
*/
if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
- blend && blend->alpha_to_coverage)
+ blend->alpha_to_coverage)
key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
/* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
- if (sctx->queued.named.blend) {
- key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
- rs->multisample_enable;
- }
+ key->part.ps.epilog.alpha_to_one = blend->alpha_to_one &&
+ rs->multisample_enable;
key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
sel->info.uses_linear_centroid +
sel->info.uses_linear_sample > 1;
- if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE])
+ if (sel->info.uses_persp_opcode_interp_sample ||
+ sel->info.uses_linear_opcode_interp_sample)
key->mono.u.ps.interpolate_at_sample_force_center = 1;
}
else
assert(0);
+ if (sel->type == PIPE_SHADER_GEOMETRY &&
+ previous_stage_sel->type == PIPE_SHADER_TESS_EVAL)
+ shader1_key.as_ngg = key->as_ngg;
+
mtx_lock(&previous_stage_sel->mutex);
ok = si_check_missing_main_part(sscreen,
previous_stage_sel,
assert(thread_index < ARRAY_SIZE(sscreen->compiler));
compiler = &sscreen->compiler[thread_index];
- if (sel->nir)
- si_lower_nir(sel);
+ if (sel->nir) {
+ /* TODO: GS always sets wave size = default. Legacy GS will have
+ * incorrect subgroup_size and ballot_bit_size. */
+ si_lower_nir(sel, si_get_wave_size(sscreen, sel->type, true, false));
+ }
/* Compile the main shader part for use with a prolog and/or epilog.
* If this fails, the driver will try to compile a monolithic shader
sel->so.num_outputs != 0,
&shader->key);
if (sscreen->info.chip_class >= GFX10 &&
- !sscreen->options.disable_ngg &&
- (((sel->type == PIPE_SHADER_VERTEX ||
- sel->type == PIPE_SHADER_TESS_EVAL) &&
+ ((sel->type == PIPE_SHADER_VERTEX &&
!shader->key.as_ls && !shader->key.as_es) ||
+ sel->type == PIPE_SHADER_TESS_EVAL ||
sel->type == PIPE_SHADER_GEOMETRY))
shader->key.as_ngg = 1;
}
}
- /* The GS copy shader is always pre-compiled.
- *
- * TODO-GFX10: We could compile the GS copy shader on demand, since it
- * is only used in the (rare) non-NGG case.
- */
- if (sel->type == PIPE_SHADER_GEOMETRY) {
+ /* The GS copy shader is always pre-compiled. */
+ if (sel->type == PIPE_SHADER_GEOMETRY &&
+ (sscreen->info.chip_class <= GFX9 || sel->tess_turns_off_ngg)) {
sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
if (!sel->gs_copy_shader) {
fprintf(stderr, "radeonsi: can't create GS copy shader\n");
sel->so = state->stream_output;
- if (state->type == PIPE_SHADER_IR_TGSI) {
+ if (state->type == PIPE_SHADER_IR_TGSI &&
+ !sscreen->options.always_nir) {
sel->tokens = tgsi_dup_tokens(state->tokens);
if (!sel->tokens) {
FREE(sel);
tgsi_scan_shader(state->tokens, &sel->info);
tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
- } else {
- assert(state->type == PIPE_SHADER_IR_NIR);
- sel->nir = state->ir.nir;
+ /* Fixup for TGSI: Set which opcode uses which (i,j) pair. */
+ if (sel->info.uses_persp_opcode_interp_centroid)
+ sel->info.uses_persp_centroid = true;
+
+ if (sel->info.uses_linear_opcode_interp_centroid)
+ sel->info.uses_linear_centroid = true;
+
+ if (sel->info.uses_persp_opcode_interp_offset ||
+ sel->info.uses_persp_opcode_interp_sample)
+ sel->info.uses_persp_center = true;
+ if (sel->info.uses_linear_opcode_interp_offset ||
+ sel->info.uses_linear_opcode_interp_sample)
+ sel->info.uses_linear_center = true;
+ } else {
+ if (state->type == PIPE_SHADER_IR_TGSI) {
+ sel->nir = tgsi_to_nir(state->tokens, ctx->screen);
+ } else {
+ assert(state->type == PIPE_SHADER_IR_NIR);
+ sel->nir = state->ir.nir;
+ }
+
+ si_nir_lower_ps_inputs(sel->nir);
si_nir_opts(sel->nir);
si_nir_scan_shader(sel->nir, &sel->info);
si_nir_scan_tess_ctrl(sel->nir, &sel->tcs_info);
!sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
!sel->so.num_outputs;
- /* Set which opcode uses which (i,j) pair. */
- if (sel->info.uses_persp_opcode_interp_centroid)
- sel->info.uses_persp_centroid = true;
-
- if (sel->info.uses_linear_opcode_interp_centroid)
- sel->info.uses_linear_centroid = true;
-
- if (sel->info.uses_persp_opcode_interp_offset ||
- sel->info.uses_persp_opcode_interp_sample)
- sel->info.uses_persp_center = true;
-
- if (sel->info.uses_linear_opcode_interp_offset ||
- sel->info.uses_linear_opcode_interp_sample)
- sel->info.uses_linear_center = true;
+ if (sel->type == PIPE_SHADER_VERTEX &&
+ sel->info.writes_edgeflag) {
+ if (sscreen->info.chip_class >= GFX10)
+ sel->ngg_writes_edgeflag = true;
+ else
+ sel->pos_writes_edgeflag = true;
+ }
switch (sel->type) {
case PIPE_SHADER_GEOMETRY:
sel->gs_input_verts_per_prim =
u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
+
+ /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
+ sel->tess_turns_off_ngg =
+ (sscreen->info.family == CHIP_NAVI10 ||
+ sscreen->info.family == CHIP_NAVI12 ||
+ sscreen->info.family == CHIP_NAVI14) &&
+ sel->gs_num_invocations * sel->gs_max_out_vertices > 256;
break;
case PIPE_SHADER_TESS_CTRL:
/* PA_CL_VS_OUT_CNTL */
bool misc_vec_ena =
- sel->info.writes_psize || sel->info.writes_edgeflag ||
+ sel->info.writes_psize || sel->pos_writes_edgeflag ||
sel->info.writes_layer || sel->info.writes_viewport_index;
sel->pa_cl_vs_out_cntl =
S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
- S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) |
+ S_02881C_USE_VTX_EDGE_FLAG(sel->pos_writes_edgeflag) |
S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
}
+ if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
+ sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
+
(void) mtx_init(&sel->mutex, mtx_plain);
si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
static bool si_update_ngg(struct si_context *sctx)
{
- if (sctx->chip_class <= GFX9 ||
- sctx->screen->options.disable_ngg)
+ if (sctx->chip_class <= GFX9)
return false;
bool new_ngg = true;
- /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
- sctx->gs_shader.cso->gs_num_invocations * sctx->gs_shader.cso->gs_max_out_vertices > 256)
+ sctx->gs_shader.cso->tess_turns_off_ngg)
new_ngg = false;
if (new_ngg != sctx->ngg) {
+ /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
+ * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
+ * pointers are set.
+ */
+ if ((sctx->family == CHIP_NAVI10 ||
+ sctx->family == CHIP_NAVI12 ||
+ sctx->family == CHIP_NAVI14) &&
+ !new_ngg)
+ sctx->flags |= SI_CONTEXT_VGT_FLUSH;
+
sctx->ngg = new_ngg;
sctx->last_rast_prim = -1; /* reset this so that it gets updated */
return true;
if (screen->info.chip_class >= GFX9)
stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
+ if (screen->info.chip_class >= GFX10 && screen->ge_wave_size == 32) {
+ stages |= S_028B54_HS_W32_EN(1) |
+ S_028B54_GS_W32_EN(key.u.ngg) | /* legacy GS only supports Wave64 */
+ S_028B54_VS_W32_EN(1);
+ }
+
si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
return pm4;
}
if (sctx->gs_shader.cso)
key.u.gs = 1;
- if (sctx->chip_class >= GFX10) {
- key.u.ngg = sctx->ngg;
-
- if (sctx->gs_shader.cso)
- key.u.streamout = !!sctx->gs_shader.cso->so.num_outputs;
- else if (sctx->tes_shader.cso)
- key.u.streamout = !!sctx->tes_shader.cso->so.num_outputs;
- else
- key.u.streamout = !!sctx->vs_shader.cso->so.num_outputs;
+ if (sctx->ngg) {
+ key.u.ngg = 1;
+ key.u.streamout = !!si_get_vs(sctx)->cso->so.num_outputs;
}
/* Update TCS and TES. */
projects / mesa.git / blobdiff