/*
* Copyright 2012 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "si_pipe.h"
-#include "sid.h"
+#include "si_build_pm4.h"
#include "gfx9d.h"
-#include "radeon/r600_cs.h"
#include "compiler/nir/nir_serialize.h"
#include "tgsi/tgsi_parse.h"
ps->info.writes_samplemask ||
alpha_to_coverage ||
si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
-
- unsigned ps_colormask = sctx->framebuffer.colorbuf_enabled_4bit &
- sctx->queued.named.blend->cb_target_mask;
- if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
- ps_colormask &= ps->colors_written_4bit;
+ unsigned ps_colormask = si_get_total_colormask(sctx);
ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
(!ps_colormask &&
}
break;
case PIPE_SHADER_TESS_CTRL:
- if (sctx->b.chip_class >= GFX9) {
+ if (sctx->chip_class >= GFX9) {
si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
key, &key->part.tcs.ls_prolog);
key->part.tcs.ls = sctx->vs_shader.cso;
}
break;
case PIPE_SHADER_GEOMETRY:
- if (sctx->b.chip_class >= GFX9) {
+ if (sctx->chip_class >= GFX9) {
if (sctx->tes_shader.cso) {
key->part.gs.es = sctx->tes_shader.cso;
} else {
* to the range supported by the type if a channel has less
* than 16 bits and the export format is 16_ABGR.
*/
- if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII) {
+ if (sctx->chip_class <= CIK && sctx->family != CHIP_HAWAII) {
key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
}
}
key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
+
+ /* ps_uses_fbfetch is true only if the color buffer is bound. */
+ if (sctx->ps_uses_fbfetch) {
+ struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
+ struct pipe_resource *tex = cb0->texture;
+
+ /* 1D textures are allocated and used as 2D on GFX9. */
+ key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
+ key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
+ (tex->target == PIPE_TEXTURE_1D ||
+ tex->target == PIPE_TEXTURE_1D_ARRAY);
+ key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
+ tex->target == PIPE_TEXTURE_2D_ARRAY ||
+ tex->target == PIPE_TEXTURE_CUBE ||
+ tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
+ tex->target == PIPE_TEXTURE_3D;
+ }
break;
}
default:
r = si_shader_create(sscreen, tm, shader, debug);
if (unlikely(r)) {
- R600_ERR("Failed to build shader variant (type=%u) %d\n",
+ PRINT_ERR("Failed to build shader variant (type=%u) %d\n",
sel->type, r);
shader->compilation_failed = true;
return;
si_nir_scan_shader(sel->nir, &sel->info);
si_nir_scan_tess_ctrl(sel->nir, &sel->info, &sel->tcs_info);
- si_lower_nir(sel, sctx->b.chip_class);
+ si_lower_nir(sel);
}
sel->type = sel->info.processor;
/* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
* conflicts, i.e. each vertex will start at a different bank.
*/
- if (sctx->b.chip_class >= GFX9)
+ if (sctx->chip_class >= GFX9)
sel->esgs_itemsize += 4;
break;
!next_hw_vs_variant ||
old_hw_vs_variant->key.opt.clip_disable !=
next_hw_vs_variant->key.opt.clip_disable))
- si_mark_atom_dirty(sctx, &sctx->clip_regs);
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
}
static void si_update_common_shader_state(struct si_context *sctx)
if (!old_sel ||
old_sel->info.colors_written != sel->info.colors_written)
- si_mark_atom_dirty(sctx, &sctx->cb_render_state);
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
if (sctx->screen->has_out_of_order_rast &&
(!old_sel ||
old_sel->info.writes_memory != sel->info.writes_memory ||
old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
- si_mark_atom_dirty(sctx, &sctx->msaa_config);
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
}
si_set_active_descriptors_for_shader(sctx, sel);
+ si_update_ps_colorbuf0_slot(sctx);
}
static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
switch (shader->selector->type) {
case PIPE_SHADER_VERTEX:
if (shader->key.as_ls) {
- assert(sctx->b.chip_class <= VI);
+ assert(sctx->chip_class <= VI);
si_pm4_delete_state(sctx, ls, shader->pm4);
} else if (shader->key.as_es) {
- assert(sctx->b.chip_class <= VI);
+ assert(sctx->chip_class <= VI);
si_pm4_delete_state(sctx, es, shader->pm4);
} else {
si_pm4_delete_state(sctx, vs, shader->pm4);
break;
case PIPE_SHADER_TESS_EVAL:
if (shader->key.as_es) {
- assert(sctx->b.chip_class <= VI);
+ assert(sctx->chip_class <= VI);
si_pm4_delete_state(sctx, es, shader->pm4);
} else {
si_pm4_delete_state(sctx, vs, shader->pm4);
return ps_input_cntl;
}
-static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
+static void si_emit_spi_map(struct si_context *sctx)
{
- struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
+ struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct si_shader *ps = sctx->ps_shader.current;
struct si_shader *vs = si_get_vs_state(sctx);
struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
/* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
* On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
*/
- unsigned gs_vertex_reuse = (sctx->b.chip_class >= VI ? 32 : 16) * num_se;
+ unsigned gs_vertex_reuse = (sctx->chip_class >= VI ? 32 : 16) * num_se;
unsigned alignment = 256 * num_se;
/* The maximum size is 63.999 MB per SE. */
unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
*
* GFX9 doesn't have the ESGS ring.
*/
- bool update_esgs = sctx->b.chip_class <= VI &&
+ bool update_esgs = sctx->chip_class <= VI &&
esgs_ring_size &&
(!sctx->esgs_ring ||
sctx->esgs_ring->width0 < esgs_ring_size);
if (update_esgs) {
pipe_resource_reference(&sctx->esgs_ring, NULL);
sctx->esgs_ring =
- si_aligned_buffer_create(sctx->b.b.screen,
- R600_RESOURCE_FLAG_UNMAPPABLE,
+ pipe_aligned_buffer_create(sctx->b.screen,
+ SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
esgs_ring_size, alignment);
if (!sctx->esgs_ring)
if (update_gsvs) {
pipe_resource_reference(&sctx->gsvs_ring, NULL);
sctx->gsvs_ring =
- si_aligned_buffer_create(sctx->b.b.screen,
- R600_RESOURCE_FLAG_UNMAPPABLE,
+ pipe_aligned_buffer_create(sctx->b.screen,
+ SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
gsvs_ring_size, alignment);
if (!sctx->gsvs_ring)
if (!pm4)
return false;
- if (sctx->b.chip_class >= CIK) {
+ if (sctx->chip_class >= CIK) {
if (sctx->esgs_ring) {
- assert(sctx->b.chip_class <= VI);
+ assert(sctx->chip_class <= VI);
si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
sctx->esgs_ring->width0 / 256);
}
}
/* Flush the context to re-emit both init_config states. */
- sctx->b.initial_gfx_cs_size = 0; /* force flush */
- si_context_gfx_flush(sctx, PIPE_FLUSH_ASYNC, NULL);
+ sctx->initial_gfx_cs_size = 0; /* force flush */
+ si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
/* Set ring bindings. */
if (sctx->esgs_ring) {
- assert(sctx->b.chip_class <= VI);
- si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
+ assert(sctx->chip_class <= VI);
+ si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
sctx->esgs_ring, 0, sctx->esgs_ring->width0,
true, true, 4, 64, 0);
- si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS,
+ si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
sctx->esgs_ring, 0, sctx->esgs_ring->width0,
false, false, 0, 0, 0);
}
if (sctx->gsvs_ring) {
- si_set_ring_buffer(&sctx->b.b, SI_RING_GSVS,
+ si_set_ring_buffer(sctx, SI_RING_GSVS,
sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
false, false, 0, 0, 0);
}
/* Create a bigger scratch buffer */
r600_resource_reference(&sctx->scratch_buffer, NULL);
- sctx->scratch_buffer = (struct r600_resource*)
+ sctx->scratch_buffer =
si_aligned_buffer_create(&sctx->screen->b,
- R600_RESOURCE_FLAG_UNMAPPABLE,
+ SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
scratch_needed_size, 256);
if (!sctx->scratch_buffer)
return false;
- si_mark_atom_dirty(sctx, &sctx->scratch_state);
- si_context_add_resource_size(&sctx->b.b,
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
+ si_context_add_resource_size(sctx,
&sctx->scratch_buffer->b.b);
}
S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
if (spi_tmpring_size != sctx->spi_tmpring_size) {
sctx->spi_tmpring_size = spi_tmpring_size;
- si_mark_atom_dirty(sctx, &sctx->scratch_state);
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
}
return true;
}
/* The address must be aligned to 2^19, because the shader only
* receives the high 13 bits.
*/
- sctx->tess_rings = si_aligned_buffer_create(sctx->b.b.screen,
- R600_RESOURCE_FLAG_32BIT,
+ sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
+ SI_RESOURCE_FLAG_32BIT,
PIPE_USAGE_DEFAULT,
sctx->screen->tess_offchip_ring_size +
sctx->screen->tess_factor_ring_size,
sctx->screen->tess_offchip_ring_size;
/* Append these registers to the init config state. */
- if (sctx->b.chip_class >= CIK) {
+ if (sctx->chip_class >= CIK) {
si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
factor_va >> 8);
- if (sctx->b.chip_class >= GFX9)
+ if (sctx->chip_class >= GFX9)
si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
S_030944_BASE_HI(factor_va >> 40));
si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
* This is done only once in a lifetime of a context.
*/
si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
- sctx->b.initial_gfx_cs_size = 0; /* force flush */
- si_context_gfx_flush(sctx, PIPE_FLUSH_ASYNC, NULL);
+ sctx->initial_gfx_cs_size = 0; /* force flush */
+ si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
}
/**
ureg_END(ureg);
sctx->fixed_func_tcs_shader.cso =
- ureg_create_shader_and_destroy(ureg, &sctx->b.b);
+ ureg_create_shader_and_destroy(ureg, &sctx->b);
}
static void si_update_vgt_shader_config(struct si_context *sctx)
S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
}
- if (sctx->b.chip_class >= GFX9)
+ if (sctx->chip_class >= GFX9)
stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
int r;
- compiler_state.chip_class = sctx->b.chip_class;
compiler_state.tm = sctx->tm;
compiler_state.debug = sctx->debug;
compiler_state.is_debug_context = sctx->is_debug;
}
/* VS as LS */
- if (sctx->b.chip_class <= VI) {
+ if (sctx->chip_class <= VI) {
r = si_shader_select(ctx, &sctx->vs_shader,
&compiler_state);
if (r)
if (sctx->gs_shader.cso) {
/* TES as ES */
- if (sctx->b.chip_class <= VI) {
+ if (sctx->chip_class <= VI) {
r = si_shader_select(ctx, &sctx->tes_shader,
&compiler_state);
if (r)
si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
}
} else if (sctx->gs_shader.cso) {
- if (sctx->b.chip_class <= VI) {
+ if (sctx->chip_class <= VI) {
/* VS as ES */
r = si_shader_select(ctx, &sctx->vs_shader,
&compiler_state);
return false;
} else {
si_pm4_bind_state(sctx, gs, NULL);
- if (sctx->b.chip_class <= VI)
+ if (sctx->chip_class <= VI)
si_pm4_bind_state(sctx, es, NULL);
}
si_update_vgt_shader_config(sctx);
if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
- si_mark_atom_dirty(sctx, &sctx->clip_regs);
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
if (sctx->ps_shader.cso) {
unsigned db_shader_control;
sctx->flatshade != rs->flatshade) {
sctx->sprite_coord_enable = rs->sprite_coord_enable;
sctx->flatshade = rs->flatshade;
- si_mark_atom_dirty(sctx, &sctx->spi_map);
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
}
if (sctx->screen->rbplus_allowed &&
(!old_ps ||
old_spi_shader_col_format !=
sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
- si_mark_atom_dirty(sctx, &sctx->cb_render_state);
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
if (sctx->ps_db_shader_control != db_shader_control) {
sctx->ps_db_shader_control = db_shader_control;
- si_mark_atom_dirty(sctx, &sctx->db_render_state);
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
if (sctx->screen->dpbb_allowed)
- si_mark_atom_dirty(sctx, &sctx->dpbb_state);
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
}
if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
- si_mark_atom_dirty(sctx, &sctx->msaa_config);
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
- if (sctx->b.chip_class == SI)
- si_mark_atom_dirty(sctx, &sctx->db_render_state);
+ if (sctx->chip_class == SI)
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
if (sctx->framebuffer.nr_samples <= 1)
- si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
+ si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
}
}
return false;
}
- if (sctx->b.chip_class >= CIK) {
+ if (sctx->chip_class >= CIK) {
if (si_pm4_state_enabled_and_changed(sctx, ls))
sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
else if (!sctx->queued.named.ls)
return true;
}
-static void si_emit_scratch_state(struct si_context *sctx,
- struct r600_atom *atom)
+static void si_emit_scratch_state(struct si_context *sctx)
{
- struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
+ struct radeon_winsys_cs *cs = sctx->gfx_cs;
radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
sctx->spi_tmpring_size);
if (sctx->scratch_buffer) {
- radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
+ radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
sctx->scratch_buffer, RADEON_USAGE_READWRITE,
RADEON_PRIO_SCRATCH_BUFFER);
}
void *si_get_blit_vs(struct si_context *sctx, enum blitter_attrib_type type,
unsigned num_layers)
{
- struct pipe_context *pipe = &sctx->b.b;
unsigned vs_blit_property;
void **vs;
}
ureg_END(ureg);
- *vs = ureg_create_shader_and_destroy(ureg, pipe);
+ *vs = ureg_create_shader_and_destroy(ureg, &sctx->b);
return *vs;
}
void si_init_shader_functions(struct si_context *sctx)
{
- si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
- si_init_atom(sctx, &sctx->scratch_state, &sctx->atoms.s.scratch_state,
- si_emit_scratch_state);
-
- sctx->b.b.create_vs_state = si_create_shader_selector;
- sctx->b.b.create_tcs_state = si_create_shader_selector;
- sctx->b.b.create_tes_state = si_create_shader_selector;
- sctx->b.b.create_gs_state = si_create_shader_selector;
- sctx->b.b.create_fs_state = si_create_shader_selector;
-
- sctx->b.b.bind_vs_state = si_bind_vs_shader;
- sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
- sctx->b.b.bind_tes_state = si_bind_tes_shader;
- sctx->b.b.bind_gs_state = si_bind_gs_shader;
- sctx->b.b.bind_fs_state = si_bind_ps_shader;
-
- sctx->b.b.delete_vs_state = si_delete_shader_selector;
- sctx->b.b.delete_tcs_state = si_delete_shader_selector;
- sctx->b.b.delete_tes_state = si_delete_shader_selector;
- sctx->b.b.delete_gs_state = si_delete_shader_selector;
- sctx->b.b.delete_fs_state = si_delete_shader_selector;
+ sctx->atoms.s.spi_map.emit = si_emit_spi_map;
+ sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
+
+ sctx->b.create_vs_state = si_create_shader_selector;
+ sctx->b.create_tcs_state = si_create_shader_selector;
+ sctx->b.create_tes_state = si_create_shader_selector;
+ sctx->b.create_gs_state = si_create_shader_selector;
+ sctx->b.create_fs_state = si_create_shader_selector;
+
+ sctx->b.bind_vs_state = si_bind_vs_shader;
+ sctx->b.bind_tcs_state = si_bind_tcs_shader;
+ sctx->b.bind_tes_state = si_bind_tes_shader;
+ sctx->b.bind_gs_state = si_bind_gs_shader;
+ sctx->b.bind_fs_state = si_bind_ps_shader;
+
+ sctx->b.delete_vs_state = si_delete_shader_selector;
+ sctx->b.delete_tcs_state = si_delete_shader_selector;
+ sctx->b.delete_tes_state = si_delete_shader_selector;
+ sctx->b.delete_gs_state = si_delete_shader_selector;
+ sctx->b.delete_fs_state = si_delete_shader_selector;
}
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