amd/registers: switch to new generated register definitions

[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c

diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index e2dc6bdabf3de55a9a1c898c437ba9be781b1585..f4569251488bae52d257d464a80aa458a1b46588 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -359,11 +359,11 @@ static void si_set_tesseval_regs(struct si_screen *sscreen, const struct si_shad
 
    if (sscreen->info.has_distributed_tess) {
       if (sscreen->info.family == CHIP_FIJI || sscreen->info.family >= CHIP_POLARIS10)
-         distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
+         distribution_mode = V_028B6C_TRAPEZOIDS;
       else
-         distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
+         distribution_mode = V_028B6C_DONUTS;
    } else
-      distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
+      distribution_mode = V_028B6C_NO_DIST;
 
    assert(pm4->shader);
    pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) | S_028B6C_PARTITIONING(partitioning) |
@@ -1215,7 +1215,7 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader
    shader->ctx_reg.ngg.pa_cl_ngg_cntl =
       S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX) |
       /* Reuse for NGG. */
-      S_028838_VERTEX_REUSE_DEPTH_GFX103(sscreen->info.chip_class >= GFX10_3 ? 30 : 0);
+      S_028838_VERTEX_REUSE_DEPTH(sscreen->info.chip_class >= GFX10_3 ? 30 : 0);
    shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(gs_sel, true);
 
    /* Oversubscribe PC. This improves performance when there are too many varyings. */