radeonsi: remove r600_pipe_common.h

[mesa.git] / src / gallium / drivers / radeonsi / si_state_streamout.c

diff --git a/src/gallium/drivers/radeonsi/si_state_streamout.c b/src/gallium/drivers/radeonsi/si_state_streamout.c
index 3d1d9dc1f0ac419ea7a0443dd977eb1579c5ec06..4cd5d2fc6b35ba3fda278fef6990cd0f555048a5 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_streamout.c
+++ b/src/gallium/drivers/radeonsi/si_state_streamout.c
@@ -1,5 +1,6 @@
 /*
  * Copyright 2013 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -21,12 +22,10 @@
  * SOFTWARE.
  */
 
-#include "si_pipe.h"
-#include "si_state.h"
-#include "sid.h"
-#include "radeon/r600_cs.h"
+#include "si_build_pm4.h"
 
 #include "util/u_memory.h"
+#include "util/u_suballoc.h"
 
 static void si_set_streamout_enable(struct si_context *sctx, bool enable);
 
@@ -51,7 +50,7 @@ si_create_so_target(struct pipe_context *ctx,
                return NULL;
        }
 
-       u_suballocator_alloc(sctx->b.allocator_zeroed_memory, 4, 4,
+       u_suballocator_alloc(sctx->allocator_zeroed_memory, 4, 4,
                             &t->buf_filled_size_offset,
                             (struct pipe_resource**)&t->buf_filled_size);
        if (!t->buf_filled_size) {
@@ -124,7 +123,7 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
                 * VS_PARTIAL_FLUSH is required if the buffers are going to be
                 * used as an input immediately.
                 */
-               sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
+               sctx->flags |= SI_CONTEXT_INV_SMEM_L1 |
                                 SI_CONTEXT_INV_VMEM_L1 |
                                 SI_CONTEXT_VS_PARTIAL_FLUSH;
        }
@@ -133,7 +132,7 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
         * start writing to the targets.
         */
        if (num_targets)
-               sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
+               sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
                                 SI_CONTEXT_CS_PARTIAL_FLUSH;
 
        /* Streamout buffers must be bound in 2 places:
@@ -152,7 +151,7 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
                if (!targets[i])
                        continue;
 
-               r600_context_add_resource_size(ctx, targets[i]->buffer);
+               si_context_add_resource_size(sctx, targets[i]->buffer);
                enabled_mask |= 1 << i;
 
                if (offsets[i] == ((unsigned)-1))
@@ -201,7 +200,7 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
                        /* Set the resource. */
                        pipe_resource_reference(&buffers->buffers[bufidx],
                                                buffer);
-                       radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
+                       radeon_add_to_gfx_buffer_list_check_mem(sctx,
                                                            (struct r600_resource*)buffer,
                                                            buffers->shader_usage,
                                                            RADEON_PRIO_SHADER_RW_BUFFER,
@@ -231,11 +230,11 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
 
 static void si_flush_vgt_streamout(struct si_context *sctx)
 {
-       struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
+       struct radeon_winsys_cs *cs = sctx->gfx_cs;
        unsigned reg_strmout_cntl;
 
        /* The register is at different places on different ASICs. */
-       if (sctx->b.chip_class >= CIK) {
+       if (sctx->chip_class >= CIK) {
                reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
                radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
        } else {
@@ -255,10 +254,9 @@ static void si_flush_vgt_streamout(struct si_context *sctx)
        radeon_emit(cs, 4); /* poll interval */
 }
 
-static void si_emit_streamout_begin(struct r600_common_context *rctx, struct r600_atom *atom)
+static void si_emit_streamout_begin(struct si_context *sctx, struct r600_atom *atom)
 {
-       struct si_context *sctx = (struct si_context*)rctx;
-       struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
+       struct radeon_winsys_cs *cs = sctx->gfx_cs;
        struct si_streamout_target **t = sctx->streamout.targets;
        uint16_t *stride_in_dw = sctx->streamout.stride_in_dw;
        unsigned i;
@@ -292,7 +290,7 @@ static void si_emit_streamout_begin(struct r600_common_context *rctx, struct r60
                        radeon_emit(cs, va); /* src address lo */
                        radeon_emit(cs, va >> 32); /* src address hi */
 
-                       radeon_add_to_buffer_list(&sctx->b,  &sctx->b.gfx,
+                       radeon_add_to_buffer_list(sctx,  sctx->gfx_cs,
                                                  t[i]->buf_filled_size,
                                                  RADEON_USAGE_READ,
                                                  RADEON_PRIO_SO_FILLED_SIZE);
@@ -313,7 +311,7 @@ static void si_emit_streamout_begin(struct r600_common_context *rctx, struct r60
 
 void si_emit_streamout_end(struct si_context *sctx)
 {
-       struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
+       struct radeon_winsys_cs *cs = sctx->gfx_cs;
        struct si_streamout_target **t = sctx->streamout.targets;
        unsigned i;
        uint64_t va;
@@ -334,7 +332,7 @@ void si_emit_streamout_end(struct si_context *sctx)
                radeon_emit(cs, 0); /* unused */
                radeon_emit(cs, 0); /* unused */
 
-               radeon_add_to_buffer_list(&sctx->b,  &sctx->b.gfx,
+               radeon_add_to_buffer_list(sctx,  sctx->gfx_cs,
                                          t[i]->buf_filled_size,
                                          RADEON_USAGE_WRITE,
                                          RADEON_PRIO_SO_FILLED_SIZE);
@@ -349,7 +347,6 @@ void si_emit_streamout_end(struct si_context *sctx)
        }
 
        sctx->streamout.begin_emitted = false;
-       sctx->b.flags |= R600_CONTEXT_STREAMOUT_FLUSH;
 }
 
 /* STREAMOUT CONFIG DERIVED STATE
@@ -359,19 +356,17 @@ void si_emit_streamout_end(struct si_context *sctx)
  * are no buffers bound.
  */
 
-static void si_emit_streamout_enable(struct r600_common_context *rctx,
+static void si_emit_streamout_enable(struct si_context *sctx,
                                     struct r600_atom *atom)
 {
-       struct si_context *sctx = (struct si_context*)rctx;
-
-       radeon_set_context_reg_seq(sctx->b.gfx.cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
-       radeon_emit(sctx->b.gfx.cs,
+       radeon_set_context_reg_seq(sctx->gfx_cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
+       radeon_emit(sctx->gfx_cs,
                    S_028B94_STREAMOUT_0_EN(si_get_strmout_en(sctx)) |
                    S_028B94_RAST_STREAM(0) |
                    S_028B94_STREAMOUT_1_EN(si_get_strmout_en(sctx)) |
                    S_028B94_STREAMOUT_2_EN(si_get_strmout_en(sctx)) |
                    S_028B94_STREAMOUT_3_EN(si_get_strmout_en(sctx)));
-       radeon_emit(sctx->b.gfx.cs,
+       radeon_emit(sctx->gfx_cs,
                    sctx->streamout.hw_enabled_mask &
                    sctx->streamout.enabled_stream_buffers_mask);
 }
@@ -412,9 +407,9 @@ void si_update_prims_generated_query_state(struct si_context *sctx,
 
 void si_init_streamout_functions(struct si_context *sctx)
 {
-       sctx->b.b.create_stream_output_target = si_create_so_target;
-       sctx->b.b.stream_output_target_destroy = si_so_target_destroy;
-       sctx->b.b.set_stream_output_targets = si_set_streamout_targets;
+       sctx->b.create_stream_output_target = si_create_so_target;
+       sctx->b.stream_output_target_destroy = si_so_target_destroy;
+       sctx->b.set_stream_output_targets = si_set_streamout_targets;
        sctx->streamout.begin_atom.emit = si_emit_streamout_begin;
        sctx->streamout.enable_atom.emit = si_emit_streamout_enable;
 }