ac/surface: add RADEON_SURF_NO_FMASK
[mesa.git] / src / gallium / drivers / radeonsi / si_texture.c
index 111607be3338e8fbc6deaf74b3f94bc785c6d419..1f7cab6b2f3d146ec4ccbcdfac28cd59e423aa34 100644 (file)
@@ -315,6 +315,8 @@ static int si_init_surface(struct si_screen *sscreen,
                flags |= RADEON_SURF_IMPORTED | RADEON_SURF_SHAREABLE;
        if (!(ptex->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING))
                flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
+       if (sscreen->debug_flags & DBG(NO_FMASK))
+               flags |= RADEON_SURF_NO_FMASK;
 
        if (sscreen->info.chip_class >= GFX10 &&
            (ptex->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING)) {
@@ -443,6 +445,13 @@ static bool si_can_disable_dcc(struct si_texture *tex)
                !(tex->buffer.external_usage & PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE));
 }
 
+static void si_texture_zero_dcc_fields(struct si_texture *tex)
+{
+       tex->dcc_offset = 0;
+       tex->display_dcc_offset = 0;
+       tex->dcc_retile_map_offset = 0;
+}
+
 static bool si_texture_discard_dcc(struct si_screen *sscreen,
                                   struct si_texture *tex)
 {
@@ -454,9 +463,7 @@ static bool si_texture_discard_dcc(struct si_screen *sscreen,
        assert(tex->dcc_separate_buffer == NULL);
 
        /* Disable DCC. */
-       tex->dcc_offset = 0;
-       tex->display_dcc_offset = 0;
-       tex->dcc_retile_map_offset = 0;
+       si_texture_zero_dcc_fields(tex);
 
        /* Notify all contexts about the change. */
        p_atomic_inc(&sscreen->dirty_tex_counter);
@@ -708,7 +715,28 @@ static void si_set_tex_bo_metadata(struct si_screen *sscreen,
        /* Clear the base address and set the relative DCC offset. */
        desc[0] = 0;
        desc[1] &= C_008F14_BASE_ADDRESS_HI;
-       desc[7] = tex->dcc_offset >> 8;
+
+       switch (sscreen->info.chip_class) {
+       case GFX6:
+       case GFX7:
+               break;
+       case GFX8:
+               desc[7] = tex->dcc_offset >> 8;
+               break;
+       case GFX9:
+               desc[7] = tex->dcc_offset >> 8;
+               desc[5] &= C_008F24_META_DATA_ADDRESS;
+               desc[5] |= S_008F24_META_DATA_ADDRESS(tex->dcc_offset >> 40);
+               break;
+       case GFX10:
+               desc[6] &= C_00A018_META_DATA_ADDRESS_LO;
+               desc[6] |= S_00A018_META_DATA_ADDRESS_LO(tex->dcc_offset >> 8);
+               desc[7] = tex->dcc_offset >> 16;
+               break;
+       default:
+               assert(0);
+       }
+
 
        /* Dwords [2:9] contain the image descriptor. */
        memcpy(&md.metadata[2], desc, sizeof(desc));
@@ -734,6 +762,9 @@ static bool si_read_tex_bo_metadata(struct si_screen *sscreen,
        if (md->size_metadata < 10 * 4 || /* at least 2(header) + 8(desc) dwords */
            md->metadata[0] == 0 || /* invalid version number */
            md->metadata[1] != si_get_bo_metadata_word1(sscreen)) /* invalid PCI ID */ {
+               /* Disable DCC because it might not be enabled. */
+               si_texture_zero_dcc_fields(tex);
+
                /* Don't report an error if the texture comes from an incompatible driver,
                 * but this might not work.
                 */
@@ -808,7 +839,7 @@ static bool si_read_tex_bo_metadata(struct si_screen *sscreen,
                /* Disable DCC. dcc_offset is always set by texture_from_handle
                 * and must be cleared here.
                 */
-               tex->dcc_offset = 0;
+               si_texture_zero_dcc_fields(tex);
        }
 
        return true;
@@ -898,8 +929,7 @@ static bool si_texture_get_handle(struct pipe_screen* screen,
                if (sscreen->ws->buffer_is_suballocated(res->buf) ||
                    tex->surface.tile_swizzle ||
                    (tex->buffer.flags & RADEON_FLAG_NO_INTERPROCESS_SHARING &&
-                    sscreen->info.has_local_buffers &&
-                    whandle->type != WINSYS_HANDLE_TYPE_KMS)) {
+                    sscreen->info.has_local_buffers)) {
                        assert(!res->b.is_shared);
                        si_reallocate_texture_inplace(sctx, tex,
                                                        PIPE_BIND_SHARED, false);
@@ -1001,8 +1031,10 @@ static bool si_texture_get_handle(struct pipe_screen* screen,
                res->external_usage = usage;
        }
 
-       return sscreen->ws->buffer_get_handle(sscreen->ws, res->buf, stride,
-                                             offset, slice_size, whandle);
+       whandle->stride = stride;
+       whandle->offset = offset + slice_size * whandle->layer;
+
+       return sscreen->ws->buffer_get_handle(sscreen->ws, res->buf, whandle);
 }
 
 static void si_texture_destroy(struct pipe_screen *screen,
@@ -1339,9 +1371,7 @@ si_texture_create_object(struct pipe_screen *screen,
                                si_texture_allocate_htile(sscreen, tex);
                }
        } else {
-               if (base->nr_samples > 1 &&
-                   !buf &&
-                   !(sscreen->debug_flags & DBG(NO_FMASK))) {
+               if (tex->surface.fmask_size) {
                        /* Allocate FMASK. */
                        tex->fmask_offset = align64(tex->size,
                                                     tex->surface.fmask_alignment);
@@ -1352,9 +1382,6 @@ si_texture_create_object(struct pipe_screen *screen,
                        tex->size = tex->cmask_offset + tex->surface.cmask_size;
                        tex->cb_color_info |= S_028C70_FAST_CLEAR(1);
                        tex->cmask_buffer = &tex->buffer;
-
-                       if (!tex->surface.fmask_size || !tex->surface.cmask_size)
-                               goto error;
                }
 
                /* Shared textures must always set up DCC here.
@@ -1764,7 +1791,6 @@ static struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen,
 {
        struct si_screen *sscreen = (struct si_screen*)screen;
        struct pb_buffer *buf = NULL;
-       unsigned stride = 0, offset = 0;
 
        /* Support only 2D textures without mipmaps */
        if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT &&
@@ -1773,13 +1799,13 @@ static struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen,
                return NULL;
 
        buf = sscreen->ws->buffer_from_handle(sscreen->ws, whandle,
-                                             sscreen->info.max_alignment,
-                                             &stride, &offset);
+                                             sscreen->info.max_alignment);
        if (!buf)
                return NULL;
 
-       return si_texture_from_winsys_buffer(sscreen, templ, buf, stride,
-                                            offset, usage, true);
+       return si_texture_from_winsys_buffer(sscreen, templ, buf,
+                                            whandle->stride, whandle->offset,
+                                            usage, true);
 }
 
 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
@@ -2586,14 +2612,12 @@ si_memobj_from_handle(struct pipe_screen *screen,
        struct si_screen *sscreen = (struct si_screen*)screen;
        struct si_memory_object *memobj = CALLOC_STRUCT(si_memory_object);
        struct pb_buffer *buf = NULL;
-       uint32_t stride, offset;
 
        if (!memobj)
                return NULL;
 
        buf = sscreen->ws->buffer_from_handle(sscreen->ws, whandle,
-                                             sscreen->info.max_alignment,
-                                             &stride, &offset);
+                                             sscreen->info.max_alignment);
        if (!buf) {
                free(memobj);
                return NULL;
@@ -2601,7 +2625,7 @@ si_memobj_from_handle(struct pipe_screen *screen,
 
        memobj->b.dedicated = dedicated;
        memobj->buf = buf;
-       memobj->stride = stride;
+       memobj->stride = whandle->stride;
 
        return (struct pipe_memory_object *)memobj;