#include <inttypes.h>
#include "state_tracker/drm_driver.h"
#include "sid.h"
+#include "amd/addrlib/inc/addrinterface.h"
static enum radeon_surf_mode
si_choose_tiling(struct si_screen *sscreen,
blit.dst.box.width = src_box->width;
blit.dst.box.height = src_box->height;
blit.dst.box.depth = src_box->depth;
- blit.mask = util_format_get_mask(src->format) &
- util_format_get_mask(dst->format);
+ blit.mask = util_format_get_mask(dst->format);
blit.filter = PIPE_TEX_FILTER_NEAREST;
if (blit.mask) {
struct pipe_resource *dst = &stransfer->staging->b.b;
struct pipe_resource *src = transfer->resource;
- if (src->nr_samples > 1) {
+ if (src->nr_samples > 1 || ((struct si_texture*)src)->is_depth) {
si_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
src, transfer->level, &transfer->box);
return;
u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
- if (dst->nr_samples > 1) {
+ if (dst->nr_samples > 1 || ((struct si_texture*)dst)->is_depth) {
si_copy_region_with_blit(ctx, dst, transfer->level,
transfer->box.x, transfer->box.y, transfer->box.z,
src, 0, &sbox);
flags |= RADEON_SURF_DISABLE_DCC;
/* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */
- if (sscreen->info.chip_class >= GFX9 &&
+ if (sscreen->info.chip_class == GFX9 &&
ptex->nr_storage_samples >= 4)
flags |= RADEON_SURF_DISABLE_DCC;
+ /* TODO: GFX10: DCC causes corruption with MSAA. */
+ if (sscreen->info.chip_class >= GFX10 &&
+ ptex->nr_storage_samples >= 2)
+ flags |= RADEON_SURF_DISABLE_DCC;
+
if (ptex->bind & PIPE_BIND_SCANOUT || is_scanout) {
/* This should catch bugs in gallium users setting incorrect flags. */
assert(ptex->nr_samples <= 1 &&
flags |= RADEON_SURF_IMPORTED | RADEON_SURF_SHAREABLE;
if (!(ptex->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING))
flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
+ if (sscreen->debug_flags & DBG(NO_FMASK))
+ flags |= RADEON_SURF_NO_FMASK;
+
+ if (sscreen->info.chip_class >= GFX10 &&
+ (ptex->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING)) {
+ flags |= RADEON_SURF_FORCE_SWIZZLE_MODE;
+ surface->u.gfx9.surf.swizzle_mode = ADDR_SW_64KB_R_X;
+ }
r = sscreen->ws->surface_init(sscreen->ws, ptex, flags, bpe,
array_mode, surface);
!(tex->buffer.external_usage & PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE));
}
+static void si_texture_zero_dcc_fields(struct si_texture *tex)
+{
+ tex->dcc_offset = 0;
+ tex->display_dcc_offset = 0;
+ tex->dcc_retile_map_offset = 0;
+}
+
static bool si_texture_discard_dcc(struct si_screen *sscreen,
struct si_texture *tex)
{
assert(tex->dcc_separate_buffer == NULL);
/* Disable DCC. */
- tex->dcc_offset = 0;
- tex->display_dcc_offset = 0;
- tex->dcc_retile_map_offset = 0;
+ si_texture_zero_dcc_fields(tex);
/* Notify all contexts about the change. */
p_atomic_inc(&sscreen->dirty_tex_counter);
bool is_array = util_texture_is_array(res->target);
uint32_t desc[8];
- si_make_texture_descriptor(sscreen, tex, true,
+ sscreen->make_texture_descriptor(sscreen, tex, true,
res->target, res->format,
swizzle, 0, res->last_level, 0,
is_array ? res->array_size - 1 : 0,
/* Clear the base address and set the relative DCC offset. */
desc[0] = 0;
desc[1] &= C_008F14_BASE_ADDRESS_HI;
- desc[7] = tex->dcc_offset >> 8;
+
+ switch (sscreen->info.chip_class) {
+ case GFX6:
+ case GFX7:
+ break;
+ case GFX8:
+ desc[7] = tex->dcc_offset >> 8;
+ break;
+ case GFX9:
+ desc[7] = tex->dcc_offset >> 8;
+ desc[5] &= C_008F24_META_DATA_ADDRESS;
+ desc[5] |= S_008F24_META_DATA_ADDRESS(tex->dcc_offset >> 40);
+ break;
+ case GFX10:
+ desc[6] &= C_00A018_META_DATA_ADDRESS_LO;
+ desc[6] |= S_00A018_META_DATA_ADDRESS_LO(tex->dcc_offset >> 8);
+ desc[7] = tex->dcc_offset >> 16;
+ break;
+ default:
+ assert(0);
+ }
+
/* Dwords [2:9] contain the image descriptor. */
memcpy(&md.metadata[2], desc, sizeof(desc));
sscreen->ws->buffer_set_metadata(tex->buffer.buf, &md);
}
-static void si_get_opaque_metadata(struct si_screen *sscreen,
- struct si_texture *tex,
- struct radeon_bo_metadata *md)
+static bool si_read_tex_bo_metadata(struct si_screen *sscreen,
+ struct si_texture *tex,
+ struct radeon_bo_metadata *md)
{
uint32_t *desc = &md->metadata[2];
- if (sscreen->info.chip_class < GFX8)
- return;
+ if (md->size_metadata < 10 * 4 || /* at least 2(header) + 8(desc) dwords */
+ md->metadata[0] == 0 || /* invalid version number */
+ md->metadata[1] != si_get_bo_metadata_word1(sscreen)) /* invalid PCI ID */ {
+ /* Disable DCC because it might not be enabled. */
+ si_texture_zero_dcc_fields(tex);
- /* Return if DCC is enabled. The texture should be set up with it
- * already.
- */
- if (md->size_metadata >= 10 * 4 && /* at least 2(header) + 8(desc) dwords */
- md->metadata[0] != 0 &&
- md->metadata[1] == si_get_bo_metadata_word1(sscreen) &&
- G_008F28_COMPRESSION_EN(desc[6])) {
- tex->dcc_offset = (uint64_t)desc[7] << 8;
+ /* Don't report an error if the texture comes from an incompatible driver,
+ * but this might not work.
+ */
+ return true;
+ }
- if (sscreen->info.chip_class >= GFX9) {
- /* Fix up parameters for displayable DCC. Some state
- * trackers don't set the SCANOUT flag when importing
- * displayable images, so we have to recover the correct
- * parameters here.
- */
+ /* Validate that sample counts and the number of mipmap levels match. */
+ unsigned last_level = G_008F1C_LAST_LEVEL(desc[3]);
+ unsigned type = G_008F1C_TYPE(desc[3]);
+
+ if (type == V_008F1C_SQ_RSRC_IMG_2D_MSAA ||
+ type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
+ unsigned log_samples =
+ util_logbase2(MAX2(1, tex->buffer.b.b.nr_storage_samples));
+
+ if (last_level != log_samples) {
+ fprintf(stderr, "radeonsi: invalid MSAA texture import, "
+ "metadata has log2(samples) = %u, the caller set %u\n",
+ last_level, log_samples);
+ return false;
+ }
+ } else {
+ if (last_level != tex->buffer.b.b.last_level) {
+ fprintf(stderr, "radeonsi: invalid mipmapped texture import, "
+ "metadata has last_level = %u, the caller set %u\n",
+ last_level, tex->buffer.b.b.last_level);
+ return false;
+ }
+ }
+
+ if (sscreen->info.chip_class >= GFX8 &&
+ G_008F28_COMPRESSION_EN(desc[6])) {
+ /* Read DCC information.
+ *
+ * Some state trackers don't set the SCANOUT flag when
+ * importing displayable images, which affects PIPE_ALIGNED
+ * and RB_ALIGNED, so we need to recover them here.
+ */
+ switch (sscreen->info.chip_class) {
+ case GFX8:
+ tex->dcc_offset = (uint64_t)desc[7] << 8;
+ break;
+
+ case GFX9:
+ tex->dcc_offset =
+ ((uint64_t)desc[7] << 8) |
+ ((uint64_t)G_008F24_META_DATA_ADDRESS(desc[5]) << 40);
tex->surface.u.gfx9.dcc.pipe_aligned =
G_008F24_META_PIPE_ALIGNED(desc[5]);
tex->surface.u.gfx9.dcc.rb_aligned =
if (!tex->surface.u.gfx9.dcc.pipe_aligned &&
!tex->surface.u.gfx9.dcc.rb_aligned)
tex->surface.is_displayable = true;
+ break;
+
+ case GFX10:
+ tex->dcc_offset =
+ ((uint64_t)G_00A018_META_DATA_ADDRESS_LO(desc[6]) << 8) |
+ ((uint64_t)desc[7] << 16);
+ tex->surface.u.gfx9.dcc.pipe_aligned =
+ G_00A018_META_PIPE_ALIGNED(desc[6]);
+ break;
+
+ default:
+ assert(0);
+ return false;
}
- return;
+ } else {
+ /* Disable DCC. dcc_offset is always set by texture_from_handle
+ * and must be cleared here.
+ */
+ si_texture_zero_dcc_fields(tex);
}
- /* Disable DCC. These are always set by texture_from_handle and must
- * be cleared here.
- */
- tex->dcc_offset = 0;
+ return true;
}
static bool si_has_displayable_dcc(struct si_texture *tex)
*poffset = offset;
}
-static boolean si_texture_get_handle(struct pipe_screen* screen,
- struct pipe_context *ctx,
- struct pipe_resource *resource,
- struct winsys_handle *whandle,
- unsigned usage)
+static bool si_texture_get_handle(struct pipe_screen* screen,
+ struct pipe_context *ctx,
+ struct pipe_resource *resource,
+ struct winsys_handle *whandle,
+ unsigned usage)
{
struct si_screen *sscreen = (struct si_screen*)screen;
struct si_context *sctx;
if (sscreen->ws->buffer_is_suballocated(res->buf) ||
tex->surface.tile_swizzle ||
(tex->buffer.flags & RADEON_FLAG_NO_INTERPROCESS_SHARING &&
- sscreen->info.has_local_buffers &&
- whandle->type != WINSYS_HANDLE_TYPE_KMS)) {
+ sscreen->info.has_local_buffers)) {
assert(!res->b.is_shared);
si_reallocate_texture_inplace(sctx, tex,
PIPE_BIND_SHARED, false);
res->external_usage = usage;
}
- return sscreen->ws->buffer_get_handle(res->buf, stride, offset,
- slice_size, whandle);
+ whandle->stride = stride;
+ whandle->offset = offset + slice_size * whandle->layer;
+
+ return sscreen->ws->buffer_get_handle(sscreen->ws, res->buf, whandle);
}
static void si_texture_destroy(struct pipe_screen *screen,
if (sscreen->info.chip_class >= GFX9) {
tex->can_sample_z = true;
tex->can_sample_s = true;
+
+ /* Stencil texturing with HTILE doesn't work
+ * with mipmapping on Navi10-14. */
+ if ((sscreen->info.family == CHIP_NAVI10 ||
+ sscreen->info.family == CHIP_NAVI12 ||
+ sscreen->info.family == CHIP_NAVI14) &&
+ base->last_level > 0)
+ tex->htile_stencil_disabled = true;
} else {
tex->can_sample_z = !tex->surface.u.legacy.depth_adjusted;
tex->can_sample_s = !tex->surface.u.legacy.stencil_adjusted;
si_texture_allocate_htile(sscreen, tex);
}
} else {
- if (base->nr_samples > 1 &&
- !buf &&
- !(sscreen->debug_flags & DBG(NO_FMASK))) {
+ if (tex->surface.fmask_size) {
/* Allocate FMASK. */
tex->fmask_offset = align64(tex->size,
tex->surface.fmask_alignment);
tex->size = tex->cmask_offset + tex->surface.cmask_size;
tex->cb_color_info |= S_028C70_FAST_CLEAR(1);
tex->cmask_buffer = &tex->buffer;
-
- if (!tex->surface.fmask_size || !tex->surface.cmask_size)
- goto error;
}
/* Shared textures must always set up DCC here.
* If it's not present, it will be disabled by
- * apply_opaque_metadata later.
+ * si_get_opaque_metadata later.
*/
if (tex->surface.dcc_size &&
(buf || !(sscreen->debug_flags & DBG(NO_DCC))) &&
tex->buffer.b.is_shared = true;
tex->buffer.external_usage = usage;
- si_get_opaque_metadata(sscreen, tex, &metadata);
+ if (!si_read_tex_bo_metadata(sscreen, tex, &metadata)) {
+ si_texture_reference(&tex, NULL);
+ return NULL;
+ }
/* Displayable DCC requires an explicit flush. */
if (dedicated &&
{
struct si_screen *sscreen = (struct si_screen*)screen;
struct pb_buffer *buf = NULL;
- unsigned stride = 0, offset = 0;
/* Support only 2D textures without mipmaps */
- if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) ||
- templ->depth0 != 1 || templ->last_level != 0)
+ if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT &&
+ templ->target != PIPE_TEXTURE_2D_ARRAY) ||
+ templ->last_level != 0)
return NULL;
buf = sscreen->ws->buffer_from_handle(sscreen->ws, whandle,
- sscreen->info.max_alignment,
- &stride, &offset);
+ sscreen->info.max_alignment);
if (!buf)
return NULL;
- return si_texture_from_winsys_buffer(sscreen, templ, buf, stride,
- offset, usage, true);
+ return si_texture_from_winsys_buffer(sscreen, templ, buf,
+ whandle->stride, whandle->offset,
+ usage, true);
}
bool si_init_flushed_depth_texture(struct pipe_context *ctx,
- struct pipe_resource *texture,
- struct si_texture **staging)
+ struct pipe_resource *texture)
{
struct si_texture *tex = (struct si_texture*)texture;
struct pipe_resource resource;
- struct si_texture **flushed_depth_texture = staging ?
- staging : &tex->flushed_depth_texture;
enum pipe_format pipe_format = texture->format;
- if (!staging) {
- if (tex->flushed_depth_texture)
- return true; /* it's ready */
-
- if (!tex->can_sample_z && tex->can_sample_s) {
- switch (pipe_format) {
- case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
- /* Save memory by not allocating the S plane. */
- pipe_format = PIPE_FORMAT_Z32_FLOAT;
- break;
- case PIPE_FORMAT_Z24_UNORM_S8_UINT:
- case PIPE_FORMAT_S8_UINT_Z24_UNORM:
- /* Save memory bandwidth by not copying the
- * stencil part during flush.
- *
- * This potentially increases memory bandwidth
- * if an application uses both Z and S texturing
- * simultaneously (a flushed Z24S8 texture
- * would be stored compactly), but how often
- * does that really happen?
- */
- pipe_format = PIPE_FORMAT_Z24X8_UNORM;
- break;
- default:;
- }
- } else if (!tex->can_sample_s && tex->can_sample_z) {
- assert(util_format_has_stencil(util_format_description(pipe_format)));
-
- /* DB->CB copies to an 8bpp surface don't work. */
- pipe_format = PIPE_FORMAT_X24S8_UINT;
+ assert(!tex->flushed_depth_texture);
+
+ if (!tex->can_sample_z && tex->can_sample_s) {
+ switch (pipe_format) {
+ case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
+ /* Save memory by not allocating the S plane. */
+ pipe_format = PIPE_FORMAT_Z32_FLOAT;
+ break;
+ case PIPE_FORMAT_Z24_UNORM_S8_UINT:
+ case PIPE_FORMAT_S8_UINT_Z24_UNORM:
+ /* Save memory bandwidth by not copying the
+ * stencil part during flush.
+ *
+ * This potentially increases memory bandwidth
+ * if an application uses both Z and S texturing
+ * simultaneously (a flushed Z24S8 texture
+ * would be stored compactly), but how often
+ * does that really happen?
+ */
+ pipe_format = PIPE_FORMAT_Z24X8_UNORM;
+ break;
+ default:;
}
+ } else if (!tex->can_sample_s && tex->can_sample_z) {
+ assert(util_format_has_stencil(util_format_description(pipe_format)));
+
+ /* DB->CB copies to an 8bpp surface don't work. */
+ pipe_format = PIPE_FORMAT_X24S8_UINT;
}
memset(&resource, 0, sizeof(resource));
resource.array_size = texture->array_size;
resource.last_level = texture->last_level;
resource.nr_samples = texture->nr_samples;
- resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_DEFAULT;
+ resource.usage = PIPE_USAGE_DEFAULT;
resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL;
resource.flags = texture->flags | SI_RESOURCE_FLAG_FLUSHED_DEPTH;
- if (staging)
- resource.flags |= SI_RESOURCE_FLAG_TRANSFER;
-
- *flushed_depth_texture = (struct si_texture *)ctx->screen->resource_create(ctx->screen, &resource);
- if (*flushed_depth_texture == NULL) {
+ tex->flushed_depth_texture = (struct si_texture *)ctx->screen->resource_create(ctx->screen, &resource);
+ if (!tex->flushed_depth_texture) {
PRINT_ERR("failed to create temporary texture to hold flushed depth\n");
return false;
}
assert(!(texture->flags & SI_RESOURCE_FLAG_TRANSFER));
assert(box->width && box->height && box->depth);
- /* Depth textures use staging unconditionally. */
- if (!tex->is_depth) {
+ if (tex->is_depth) {
+ /* Depth textures use staging unconditionally. */
+ use_staging_texture = true;
+ } else {
/* Degrade the tile mode if we get too many transfers on APUs.
* On dGPUs, the staging texture is always faster.
* Only count uploads that are at least 4x4 pixels large.
trans->b.b.usage = usage;
trans->b.b.box = *box;
- if (tex->is_depth) {
- struct si_texture *staging_depth;
-
- if (tex->buffer.b.b.nr_samples > 1) {
- /* MSAA depth buffers need to be converted to single sample buffers.
- *
- * Mapping MSAA depth buffers can occur if ReadPixels is called
- * with a multisample GLX visual.
- *
- * First downsample the depth buffer to a temporary texture,
- * then decompress the temporary one to staging.
- *
- * Only the region being mapped is transfered.
- */
- struct pipe_resource resource;
-
- si_init_temp_resource_from_box(&resource, texture, box, level, 0);
-
- if (!si_init_flushed_depth_texture(ctx, &resource, &staging_depth)) {
- PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
- goto fail_trans;
- }
-
- if (usage & PIPE_TRANSFER_READ) {
- struct pipe_resource *temp = ctx->screen->resource_create(ctx->screen, &resource);
- if (!temp) {
- PRINT_ERR("failed to create a temporary depth texture\n");
- goto fail_trans;
- }
-
- si_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
- si_blit_decompress_depth(ctx, (struct si_texture*)temp, staging_depth,
- 0, 0, 0, box->depth, 0, 0);
- pipe_resource_reference(&temp, NULL);
- }
-
- /* Just get the strides. */
- si_texture_get_offset(sctx->screen, staging_depth, level, NULL,
- &trans->b.b.stride,
- &trans->b.b.layer_stride);
- } else {
- /* XXX: only readback the rectangle which is being mapped? */
- /* XXX: when discard is true, no need to read back from depth texture */
- if (!si_init_flushed_depth_texture(ctx, texture, &staging_depth)) {
- PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
- goto fail_trans;
- }
-
- si_blit_decompress_depth(ctx, tex, staging_depth,
- level, level,
- box->z, box->z + box->depth - 1,
- 0, 0);
-
- offset = si_texture_get_offset(sctx->screen, staging_depth,
- level, box,
- &trans->b.b.stride,
- &trans->b.b.layer_stride);
- }
-
- trans->staging = &staging_depth->buffer;
- buf = trans->staging;
- } else if (use_staging_texture) {
+ if (use_staging_texture) {
struct pipe_resource resource;
struct si_texture *staging;
resource.usage = (usage & PIPE_TRANSFER_READ) ?
PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
+ /* Since depth-stencil textures don't support linear tiling,
+ * blit from ZS to color and vice versa. u_blitter will do
+ * the packing for these formats.
+ */
+ if (tex->is_depth)
+ resource.format = util_blitter_get_color_format_for_zs(resource.format);
+
/* Create the temporary texture. */
staging = (struct si_texture*)ctx->screen->resource_create(ctx->screen, &resource);
if (!staging) {
sctx->ws->buffer_unmap(buf->buf);
}
- if ((transfer->usage & PIPE_TRANSFER_WRITE) && stransfer->staging) {
- if (tex->is_depth && tex->buffer.b.b.nr_samples <= 1) {
- ctx->resource_copy_region(ctx, texture, transfer->level,
- transfer->box.x, transfer->box.y, transfer->box.z,
- &stransfer->staging->b.b, transfer->level,
- &transfer->box);
- } else {
- si_copy_from_staging_texture(ctx, stransfer);
- }
- }
+ if ((transfer->usage & PIPE_TRANSFER_WRITE) && stransfer->staging)
+ si_copy_from_staging_texture(ctx, stransfer);
if (stransfer->staging) {
sctx->num_alloc_tex_transfer_bytes += stransfer->staging->buf->size;
/* Return if it's allowed to reinterpret one format as another with DCC enabled.
*/
-bool vi_dcc_formats_compatible(enum pipe_format format1,
+bool vi_dcc_formats_compatible(struct si_screen *sscreen,
+ enum pipe_format format1,
enum pipe_format format2)
{
const struct util_format_description *desc1, *desc2;
/* If the clear values are all 1 or all 0, this constraint can be
* ignored. */
- if (vi_alpha_is_on_msb(format1) != vi_alpha_is_on_msb(format2))
+ if (vi_alpha_is_on_msb(sscreen, format1) != vi_alpha_is_on_msb(sscreen, format2))
return false;
/* Channel types must match if the clear value of 1 is used.
struct si_texture *stex = (struct si_texture *)tex;
return vi_dcc_enabled(stex, level) &&
- !vi_dcc_formats_compatible(tex->format, view_format);
+ !vi_dcc_formats_compatible((struct si_screen*)tex->screen,
+ tex->format, view_format);
}
/* This can't be merged with the above function, because
struct si_screen *sscreen = (struct si_screen*)screen;
struct si_memory_object *memobj = CALLOC_STRUCT(si_memory_object);
struct pb_buffer *buf = NULL;
- uint32_t stride, offset;
if (!memobj)
return NULL;
buf = sscreen->ws->buffer_from_handle(sscreen->ws, whandle,
- sscreen->info.max_alignment,
- &stride, &offset);
+ sscreen->info.max_alignment);
if (!buf) {
free(memobj);
return NULL;
memobj->b.dedicated = dedicated;
memobj->buf = buf;
- memobj->stride = stride;
+ memobj->stride = whandle->stride;
return (struct pipe_memory_object *)memobj;
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