radeonsi: fix doubles and int64

[mesa.git] / src / gallium / drivers / radeonsi / si_texture.c

diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index bbd87ee0b5fea10a4a5584a3a0f92ed77c8f3e34..bcf9187082bceea68b1767aaf55158c6172a7451 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -25,7 +25,7 @@
 
 #include "si_pipe.h"
 #include "si_query.h"
-#include "util/u_format.h"
+#include "util/format/u_format.h"
 #include "util/u_log.h"
 #include "util/u_memory.h"
 #include "util/u_pack_color.h"
@@ -53,7 +53,7 @@ bool si_prepare_for_dma_blit(struct si_context *sctx,
                             unsigned src_level,
                             const struct pipe_box *src_box)
 {
-       if (!sctx->dma_cs)
+       if (!sctx->sdma_cs)
                return false;
 
        if (dst->surface.bpe != src->surface.bpe)
@@ -199,7 +199,8 @@ static unsigned si_texture_get_offset(struct si_screen *sscreen,
 
                /* Each texture is an array of slices. Each slice is an array
                 * of mipmap levels. */
-               return box->z * tex->surface.u.gfx9.surf_slice_size +
+               return tex->surface.u.gfx9.surf_offset +
+                      box->z * tex->surface.u.gfx9.surf_slice_size +
                       tex->surface.u.gfx9.offset[level] +
                       (box->y / tex->surface.blk_h *
                        tex->surface.u.gfx9.surf_pitch +
@@ -292,7 +293,9 @@ static int si_init_surface(struct si_screen *sscreen,
 
        /* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */
        if (sscreen->info.chip_class == GFX9 &&
-           ptex->nr_storage_samples >= 4)
+           (ptex->nr_storage_samples >= 4 ||
+            (sscreen->info.family == CHIP_RAVEN &&
+             ptex->nr_storage_samples >= 2 && bpe < 4)))
                flags |= RADEON_SURF_DISABLE_DCC;
 
        /* TODO: GFX10: DCC causes corruption with MSAA. */
@@ -307,7 +310,7 @@ static int si_init_surface(struct si_screen *sscreen,
        if (!is_imported && (sscreen->debug_flags & DBG(NO_DCC)))
                flags |= RADEON_SURF_DISABLE_DCC;
 
-       if (ptex->bind & PIPE_BIND_SCANOUT || is_scanout) {
+       if (is_scanout) {
                /* This should catch bugs in gallium users setting incorrect flags. */
                assert(ptex->nr_samples <= 1 &&
                       ptex->array_size == 1 &&
@@ -327,6 +330,12 @@ static int si_init_surface(struct si_screen *sscreen,
        if (sscreen->debug_flags & DBG(NO_FMASK))
                flags |= RADEON_SURF_NO_FMASK;
 
+       if (sscreen->info.chip_class == GFX9 &&
+           (ptex->flags & SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE)) {
+               flags |= RADEON_SURF_FORCE_MICRO_TILE_MODE;
+               surface->micro_tile_mode = SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(ptex->flags);
+       }
+
        if (sscreen->info.chip_class >= GFX10 &&
            (ptex->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING)) {
                flags |= RADEON_SURF_FORCE_SWIZZLE_MODE;
@@ -371,10 +380,8 @@ static void si_get_display_metadata(struct si_screen *sscreen,
                else
                        *array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
 
-               *is_scanout = metadata->u.gfx9.swizzle_mode == 0 ||
-                             metadata->u.gfx9.swizzle_mode % 4 == 2;
-
                surf->u.gfx9.surf.swizzle_mode = metadata->u.gfx9.swizzle_mode;
+               *is_scanout = metadata->u.gfx9.scanout;
 
                if (metadata->u.gfx9.dcc_offset_256B) {
                        surf->u.gfx9.display_dcc_pitch_max = metadata->u.gfx9.dcc_pitch_max;
@@ -461,10 +468,8 @@ static void si_texture_zero_dcc_fields(struct si_texture *tex)
 static bool si_texture_discard_dcc(struct si_screen *sscreen,
                                   struct si_texture *tex)
 {
-       if (!si_can_disable_dcc(tex)) {
-               assert(tex->surface.display_dcc_offset == 0);
+       if (!si_can_disable_dcc(tex))
                return false;
-       }
 
        assert(tex->dcc_separate_buffer == NULL);
 
@@ -619,6 +624,7 @@ static void si_reallocate_texture_inplace(struct si_context *sctx,
        tex->can_sample_s = new_tex->can_sample_s;
 
        tex->separate_dcc_dirty = new_tex->separate_dcc_dirty;
+       tex->displayable_dcc_dirty = new_tex->displayable_dcc_dirty;
        tex->dcc_gather_statistics = new_tex->dcc_gather_statistics;
        si_resource_reference(&tex->dcc_separate_buffer,
                                new_tex->dcc_separate_buffer);
@@ -654,6 +660,7 @@ static void si_set_tex_bo_metadata(struct si_screen *sscreen,
 
        if (sscreen->info.chip_class >= GFX9) {
                md.u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
+               md.u.gfx9.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
 
                if (tex->surface.dcc_offset && !tex->dcc_separate_buffer) {
                        uint64_t dcc_offset =
@@ -804,12 +811,7 @@ static bool si_read_tex_bo_metadata(struct si_screen *sscreen,
 
        if (sscreen->info.chip_class >= GFX8 &&
            G_008F28_COMPRESSION_EN(desc[6])) {
-               /* Read DCC information.
-                *
-                * Some state trackers don't set the SCANOUT flag when
-                * importing displayable images, which affects PIPE_ALIGNED
-                * and RB_ALIGNED, so we need to recover them here.
-                */
+               /* Read DCC information. */
                switch (sscreen->info.chip_class) {
                case GFX8:
                        tex->surface.dcc_offset = (uint64_t)desc[7] << 8;
@@ -827,7 +829,7 @@ static bool si_read_tex_bo_metadata(struct si_screen *sscreen,
                        /* If DCC is unaligned, this can only be a displayable image. */
                        if (!tex->surface.u.gfx9.dcc.pipe_aligned &&
                            !tex->surface.u.gfx9.dcc.rb_aligned)
-                               tex->surface.is_displayable = true;
+                               assert(tex->surface.is_displayable);
                        break;
 
                case GFX10:
@@ -1517,14 +1519,12 @@ si_texture_create_object(struct pipe_screen *screen,
 
                        /* Copy the staging buffer to the buffer backing the texture. */
                        struct si_context *sctx = (struct si_context*)sscreen->aux_context;
-                       struct pipe_box box;
-                       u_box_1d(0, buf->b.b.width0, &box);
 
                        assert(tex->surface.dcc_retile_map_offset <= UINT_MAX);
                        simple_mtx_lock(&sscreen->aux_context_lock);
-                       sctx->dma_copy(&sctx->b, &tex->buffer.b.b, 0,
-                                      tex->surface.dcc_retile_map_offset, 0, 0,
-                                      &buf->b.b, 0, &box);
+                       si_sdma_copy_buffer(sctx, &tex->buffer.b.b, &buf->b.b,
+                                           tex->surface.dcc_retile_map_offset,
+                                           0, buf->b.b.width0);
                        sscreen->aux_context->flush(sscreen->aux_context, NULL, 0);
                        simple_mtx_unlock(&sscreen->aux_context_lock);
 
@@ -1697,7 +1697,8 @@ struct pipe_resource *si_texture_create(struct pipe_screen *screen,
                        plane_templ[i].bind |= PIPE_BIND_SHARED;
 
                if (si_init_surface(sscreen, &surface[i], &plane_templ[i],
-                                   tile_mode, 0, false, false,
+                                   tile_mode, 0, false,
+                                   plane_templ[i].bind & PIPE_BIND_SCANOUT,
                                    is_flushed_depth, tc_compatible_htile))
                        return NULL;
 
@@ -1721,10 +1722,12 @@ struct pipe_resource *si_texture_create(struct pipe_screen *screen,
                tex->plane_index = i;
                tex->num_planes = num_planes;
 
-               if (!last_plane)
+               if (!plane0) {
                        plane0 = last_plane = tex;
-               else
+               } else {
                        last_plane->buffer.b.b.next = &tex->buffer.b.b;
+                       last_plane = tex;
+               }
        }
 
        return (struct pipe_resource *)plane0;