* dst: If overwriting the whole texture, discard CMASK and use
* SDMA. Otherwise, use the 3D path.
*/
- if (dst->cmask.size && dst->dirty_level_mask & (1 << dst_level)) {
+ if (dst->cmask_buffer && dst->dirty_level_mask & (1 << dst_level)) {
/* The CMASK clear is only enabled for the first level. */
assert(dst_level == 0);
if (!util_texrange_covers_whole_level(&dst->buffer.b.b, dst_level,
}
/* All requirements are met. Prepare textures for SDMA. */
- if (src->cmask.size && src->dirty_level_mask & (1 << src_level))
+ if (src->cmask_buffer && src->dirty_level_mask & (1 << src_level))
sctx->b.flush_resource(&sctx->b, &src->buffer.b.b);
assert(!(src->dirty_level_mask & (1 << src_level)));
}
/* Copy from a full GPU texture to a transfer's staging one. */
-static void si_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
+static void si_copy_to_staging_texture(struct pipe_context *ctx, struct si_transfer *stransfer)
{
struct si_context *sctx = (struct si_context*)ctx;
- struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
- struct pipe_resource *dst = &rtransfer->staging->b.b;
+ struct pipe_transfer *transfer = (struct pipe_transfer*)stransfer;
+ struct pipe_resource *dst = &stransfer->staging->b.b;
struct pipe_resource *src = transfer->resource;
if (src->nr_samples > 1) {
}
/* Copy from a transfer's staging texture to a full GPU one. */
-static void si_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer)
+static void si_copy_from_staging_texture(struct pipe_context *ctx, struct si_transfer *stransfer)
{
struct si_context *sctx = (struct si_context*)ctx;
- struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
+ struct pipe_transfer *transfer = (struct pipe_transfer*)stransfer;
struct pipe_resource *dst = transfer->resource;
- struct pipe_resource *src = &rtransfer->staging->b.b;
+ struct pipe_resource *src = &stransfer->staging->b.b;
struct pipe_box sbox;
u_box_3d(0, 0, 0, transfer->box.width, transfer->box.height, transfer->box.depth, &sbox);
static int si_init_surface(struct si_screen *sscreen,
struct radeon_surf *surface,
const struct pipe_resource *ptex,
- unsigned num_color_samples,
enum radeon_surf_mode array_mode,
unsigned pitch_in_bytes_override,
unsigned offset,
if (!is_flushed_depth &&
ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
- bpe = 4; /* stencil is allocated separately on evergreen */
+ bpe = 4; /* stencil is allocated separately */
} else {
bpe = util_format_get_blocksize(ptex->format);
assert(util_is_power_of_two_or_zero(bpe));
/* VI: DCC clear for 4x and 8x MSAA array textures unimplemented. */
if (sscreen->info.chip_class == VI &&
- num_color_samples >= 4 &&
+ ptex->nr_storage_samples >= 4 &&
ptex->array_size > 1)
flags |= RADEON_SURF_DISABLE_DCC;
/* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */
if (sscreen->info.chip_class >= GFX9 &&
- num_color_samples >= 4)
+ ptex->nr_storage_samples >= 4)
flags |= RADEON_SURF_DISABLE_DCC;
if (ptex->bind & PIPE_BIND_SCANOUT || is_scanout) {
flags |= RADEON_SURF_SHAREABLE;
if (is_imported)
flags |= RADEON_SURF_IMPORTED | RADEON_SURF_SHAREABLE;
- if (!(ptex->flags & SI_RESOURCE_FLAG_FORCE_TILING))
+ if (!(ptex->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING))
flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
- r = sscreen->ws->surface_init(sscreen->ws, ptex, num_color_samples,
- flags, bpe, array_mode, surface);
+ r = sscreen->ws->surface_init(sscreen->ws, ptex, flags, bpe,
+ array_mode, surface);
if (r) {
return r;
}
void si_texture_discard_cmask(struct si_screen *sscreen,
struct si_texture *tex)
{
- if (!tex->cmask.size)
+ if (!tex->cmask_buffer)
return;
assert(tex->buffer.b.b.nr_samples <= 1);
/* Disable CMASK. */
- memset(&tex->cmask, 0, sizeof(tex->cmask));
- tex->cmask.base_address_reg = tex->buffer.gpu_address >> 8;
+ tex->cmask_base_address_reg = tex->buffer.gpu_address >> 8;
tex->dirty_level_mask = 0;
tex->cb_color_info &= ~S_028C70_FAST_CLEAR(1);
if (tex->cmask_buffer != &tex->buffer)
r600_resource_reference(&tex->cmask_buffer, NULL);
+ tex->cmask_buffer = NULL;
+
/* Notify all contexts about the change. */
p_atomic_inc(&sscreen->dirty_tex_counter);
p_atomic_inc(&sscreen->compressed_colortex_counter);
/* We can't disable DCC if it can be written by another process. */
return tex->dcc_offset &&
(!tex->buffer.b.is_shared ||
- !(tex->buffer.external_usage & PIPE_HANDLE_USAGE_WRITE));
+ !(tex->buffer.external_usage & PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE));
}
static bool si_texture_discard_dcc(struct si_screen *sscreen,
new_tex->flushed_depth_texture);
tex->fmask_offset = new_tex->fmask_offset;
- tex->cmask = new_tex->cmask;
- r600_resource_reference(&tex->cmask_buffer, new_tex->cmask_buffer);
+ tex->cmask_offset = new_tex->cmask_offset;
+ tex->cmask_base_address_reg = new_tex->cmask_base_address_reg;
+
+ if (tex->cmask_buffer == &tex->buffer)
+ tex->cmask_buffer = NULL;
+ else
+ r600_resource_reference(&tex->cmask_buffer, NULL);
+
+ if (new_tex->cmask_buffer == &new_tex->buffer)
+ tex->cmask_buffer = &tex->buffer;
+ else
+ r600_resource_reference(&tex->cmask_buffer, new_tex->cmask_buffer);
+
tex->dcc_offset = new_tex->dcc_offset;
tex->cb_color_info = new_tex->cb_color_info;
memcpy(tex->color_clear_value, new_tex->color_clear_value,
if (new_bind_flag == PIPE_BIND_LINEAR) {
assert(!tex->htile_offset);
- assert(!tex->cmask.size);
+ assert(!tex->cmask_buffer);
assert(!tex->surface.fmask_size);
assert(!tex->dcc_offset);
assert(!tex->is_depth);
* disable it for external clients that want write
* access.
*/
- if (usage & PIPE_HANDLE_USAGE_WRITE && tex->dcc_offset) {
+ if (usage & PIPE_HANDLE_USAGE_SHADER_WRITE && tex->dcc_offset) {
if (si_texture_disable_dcc(sctx, tex)) {
update_metadata = true;
/* si_texture_disable_dcc flushes the context */
}
if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) &&
- (tex->cmask.size || tex->dcc_offset)) {
+ (tex->cmask_buffer || tex->dcc_offset)) {
/* Eliminate fast clear (both CMASK and DCC) */
si_eliminate_fast_color_clear(sctx, tex);
/* eliminate_fast_color_clear flushes the context */
/* Disable CMASK if flush_resource isn't going
* to be called.
*/
- if (tex->cmask.size)
+ if (tex->cmask_buffer)
si_texture_discard_cmask(sscreen, tex);
}
static const struct u_resource_vtbl si_texture_vtbl;
-void si_texture_get_cmask_info(struct si_screen *sscreen,
- struct si_texture *tex,
- struct r600_cmask_info *out)
-{
- unsigned pipe_interleave_bytes = sscreen->info.pipe_interleave_bytes;
- unsigned num_pipes = sscreen->info.num_tile_pipes;
- unsigned cl_width, cl_height;
-
- if (sscreen->info.chip_class >= GFX9) {
- out->alignment = tex->surface.u.gfx9.cmask_alignment;
- out->size = tex->surface.u.gfx9.cmask_size;
- return;
- }
-
- switch (num_pipes) {
- case 2:
- cl_width = 32;
- cl_height = 16;
- break;
- case 4:
- cl_width = 32;
- cl_height = 32;
- break;
- case 8:
- cl_width = 64;
- cl_height = 32;
- break;
- case 16: /* Hawaii */
- cl_width = 64;
- cl_height = 64;
- break;
- default:
- assert(0);
- return;
- }
-
- unsigned base_align = num_pipes * pipe_interleave_bytes;
-
- unsigned width = align(tex->buffer.b.b.width0, cl_width*8);
- unsigned height = align(tex->buffer.b.b.height0, cl_height*8);
- unsigned slice_elements = (width * height) / (8*8);
-
- /* Each element of CMASK is a nibble. */
- unsigned slice_bytes = slice_elements / 2;
-
- out->slice_tile_max = (width * height) / (128*128);
- if (out->slice_tile_max)
- out->slice_tile_max -= 1;
-
- out->alignment = MAX2(256, base_align);
- out->size = util_num_layers(&tex->buffer.b.b, 0) *
- align(slice_bytes, base_align);
-}
-
-static void si_texture_allocate_cmask(struct si_screen *sscreen,
- struct si_texture *tex)
-{
- si_texture_get_cmask_info(sscreen, tex, &tex->cmask);
-
- tex->cmask.offset = align64(tex->size, tex->cmask.alignment);
- tex->size = tex->cmask.offset + tex->cmask.size;
-
- tex->cb_color_info |= S_028C70_FAST_CLEAR(1);
-}
-
static void si_texture_get_htile_size(struct si_screen *sscreen,
struct si_texture *tex)
{
return;
}
- width = align(tex->buffer.b.b.width0, cl_width * 8);
- height = align(tex->buffer.b.b.height0, cl_height * 8);
+ width = align(tex->surface.u.legacy.level[0].nblk_x, cl_width * 8);
+ height = align(tex->surface.u.legacy.level[0].nblk_y, cl_height * 8);
slice_elements = (width * height) / (8 * 8);
slice_bytes = slice_elements * 4;
tex->surface.u.gfx9.fmask.epitch);
}
- if (tex->cmask.size) {
- u_log_printf(log, " CMask: offset=%"PRIu64", size=%"PRIu64", "
+ if (tex->cmask_buffer) {
+ u_log_printf(log, " CMask: offset=%"PRIu64", size=%u, "
"alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
- tex->cmask.offset,
- tex->surface.u.gfx9.cmask_size,
- tex->surface.u.gfx9.cmask_alignment,
+ tex->cmask_offset,
+ tex->surface.cmask_size,
+ tex->surface.cmask_alignment,
tex->surface.u.gfx9.cmask.rb_aligned,
tex->surface.u.gfx9.cmask.pipe_aligned);
}
tex->surface.u.legacy.fmask.slice_tile_max,
tex->surface.u.legacy.fmask.tiling_index);
- if (tex->cmask.size)
- u_log_printf(log, " CMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, "
+ if (tex->cmask_buffer)
+ u_log_printf(log, " CMask: offset=%"PRIu64", size=%u, alignment=%u, "
"slice_tile_max=%u\n",
- tex->cmask.offset, tex->cmask.size, tex->cmask.alignment,
- tex->cmask.slice_tile_max);
+ tex->cmask_offset, tex->surface.cmask_size, tex->surface.cmask_alignment,
+ tex->surface.u.legacy.cmask_slice_tile_max);
if (tex->htile_offset)
u_log_printf(log, " HTile: offset=%"PRIu64", size=%u, "
static struct si_texture *
si_texture_create_object(struct pipe_screen *screen,
const struct pipe_resource *base,
- unsigned num_color_samples,
struct pb_buffer *buf,
struct radeon_surf *surface)
{
tex->surface = *surface;
tex->size = tex->surface.surf_size;
- tex->num_color_samples = num_color_samples;
tex->tc_compatible_htile = tex->surface.htile_size != 0 &&
(tex->surface.flags &
tex->surface.fmask_alignment);
tex->size = tex->fmask_offset + tex->surface.fmask_size;
- si_texture_allocate_cmask(sscreen, tex);
+ /* Allocate CMASK. */
+ tex->cmask_offset = align64(tex->size, tex->surface.cmask_alignment);
+ tex->size = tex->cmask_offset + tex->surface.cmask_size;
+ tex->cb_color_info |= S_028C70_FAST_CLEAR(1);
tex->cmask_buffer = &tex->buffer;
- if (!tex->surface.fmask_size || !tex->cmask.size) {
+ if (!tex->surface.fmask_size || !tex->surface.cmask_size) {
FREE(tex);
return NULL;
}
resource->gart_usage = buf->size;
}
- if (tex->cmask.size) {
+ if (tex->cmask_buffer) {
/* Initialize the cmask to 0xCC (= compressed state). */
si_screen_clear_buffer(sscreen, &tex->cmask_buffer->b.b,
- tex->cmask.offset, tex->cmask.size,
+ tex->cmask_offset, tex->surface.cmask_size,
0xCCCCCCCC);
}
if (tex->htile_offset) {
}
/* Initialize the CMASK base register value. */
- tex->cmask.base_address_reg =
- (tex->buffer.gpu_address + tex->cmask.offset) >> 8;
+ tex->cmask_base_address_reg =
+ (tex->buffer.gpu_address + tex->cmask_offset) >> 8;
if (sscreen->debug_flags & DBG(VM)) {
fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
const struct pipe_resource *templ, bool tc_compatible_htile)
{
const struct util_format_description *desc = util_format_description(templ->format);
- bool force_tiling = templ->flags & SI_RESOURCE_FLAG_FORCE_TILING;
+ bool force_tiling = templ->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING;
bool is_depth_stencil = util_format_is_depth_or_stencil(templ->format) &&
!(templ->flags & SI_RESOURCE_FLAG_FLUSHED_DEPTH);
return RADEON_SURF_MODE_2D;
}
-static unsigned si_get_num_color_samples(struct si_screen *sscreen,
- const struct pipe_resource *templ,
- bool imported)
-{
- if (!imported && templ->nr_samples >= 2 &&
- sscreen->eqaa_force_color_samples)
- return sscreen->eqaa_force_color_samples;
-
- return CLAMP(templ->nr_samples, 1, 8);
-}
-
struct pipe_resource *si_texture_create(struct pipe_screen *screen,
const struct pipe_resource *templ)
{
*/
if (is_zs && sscreen->eqaa_force_z_samples) {
((struct pipe_resource*)templ)->nr_samples =
+ ((struct pipe_resource*)templ)->nr_storage_samples =
sscreen->eqaa_force_z_samples;
} else if (!is_zs && sscreen->eqaa_force_color_samples) {
((struct pipe_resource*)templ)->nr_samples =
sscreen->eqaa_force_coverage_samples;
+ ((struct pipe_resource*)templ)->nr_storage_samples =
+ sscreen->eqaa_force_color_samples;
}
}
!is_flushed_depth &&
templ->nr_samples <= 1 && /* TC-compat HTILE is less efficient with MSAA */
is_zs;
- unsigned num_color_samples = si_get_num_color_samples(sscreen, templ, false);
int r;
- r = si_init_surface(sscreen, &surface, templ, num_color_samples,
+ r = si_init_surface(sscreen, &surface, templ,
si_choose_tiling(sscreen, templ, tc_compatible_htile),
0, 0, false, false, is_flushed_depth,
tc_compatible_htile);
}
return (struct pipe_resource *)
- si_texture_create_object(screen, templ, num_color_samples,
- NULL, &surface);
+ si_texture_create_object(screen, templ, NULL, &surface);
}
static struct pipe_resource *si_texture_from_winsys_buffer(struct si_screen *sscreen,
is_scanout = false;
}
- unsigned num_color_samples = si_get_num_color_samples(sscreen, templ, true);
-
- r = si_init_surface(sscreen, &surface, templ, num_color_samples,
+ r = si_init_surface(sscreen, &surface, templ,
array_mode, stride, offset, true, is_scanout,
false, false);
if (r)
return NULL;
- tex = si_texture_create_object(&sscreen->b, templ, num_color_samples,
- buf, &surface);
+ tex = si_texture_create_object(&sscreen->b, templ, buf, &surface);
if (!tex)
return NULL;
templ->depth0 != 1 || templ->last_level != 0)
return NULL;
- buf = sscreen->ws->buffer_from_handle(sscreen->ws, whandle, &stride, &offset);
+ buf = sscreen->ws->buffer_from_handle(sscreen->ws, whandle,
+ sscreen->info.max_alignment,
+ &stride, &offset);
if (!buf)
return NULL;
si_alloc_resource(sscreen, &tex->buffer);
/* Initialize the CMASK base address (needed even without CMASK). */
- tex->cmask.base_address_reg =
- (tex->buffer.gpu_address + tex->cmask.offset) >> 8;
+ tex->cmask_base_address_reg =
+ (tex->buffer.gpu_address + tex->cmask_offset) >> 8;
p_atomic_inc(&sscreen->dirty_tex_counter);
{
struct si_context *sctx = (struct si_context*)ctx;
struct si_texture *tex = (struct si_texture*)texture;
- struct r600_transfer *trans;
+ struct si_transfer *trans;
struct r600_resource *buf;
unsigned offset = 0;
char *map;
}
}
- trans = CALLOC_STRUCT(r600_transfer);
+ trans = CALLOC_STRUCT(si_transfer);
if (!trans)
return NULL;
pipe_resource_reference(&trans->b.b.resource, texture);
buf = &tex->buffer;
}
+ /* Always unmap texture CPU mappings on 32-bit architectures, so that
+ * we don't run out of the CPU address space.
+ */
+ if (sizeof(void*) == 4)
+ usage |= RADEON_TRANSFER_TEMPORARY;
+
if (!(map = si_buffer_map_sync_with_rings(sctx, buf, usage)))
goto fail_trans;
struct pipe_transfer* transfer)
{
struct si_context *sctx = (struct si_context*)ctx;
- struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
+ struct si_transfer *stransfer = (struct si_transfer*)transfer;
struct pipe_resource *texture = transfer->resource;
struct si_texture *tex = (struct si_texture*)texture;
- if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) {
+ /* Always unmap texture CPU mappings on 32-bit architectures, so that
+ * we don't run out of the CPU address space.
+ */
+ if (sizeof(void*) == 4) {
+ struct r600_resource *buf =
+ stransfer->staging ? stransfer->staging : &tex->buffer;
+
+ sctx->ws->buffer_unmap(buf->buf);
+ }
+
+ if ((transfer->usage & PIPE_TRANSFER_WRITE) && stransfer->staging) {
if (tex->is_depth && tex->buffer.b.b.nr_samples <= 1) {
ctx->resource_copy_region(ctx, texture, transfer->level,
transfer->box.x, transfer->box.y, transfer->box.z,
- &rtransfer->staging->b.b, transfer->level,
+ &stransfer->staging->b.b, transfer->level,
&transfer->box);
} else {
- si_copy_from_staging_texture(ctx, rtransfer);
+ si_copy_from_staging_texture(ctx, stransfer);
}
}
- if (rtransfer->staging) {
- sctx->num_alloc_tex_transfer_bytes += rtransfer->staging->buf->size;
- r600_resource_reference(&rtransfer->staging, NULL);
+ if (stransfer->staging) {
+ sctx->num_alloc_tex_transfer_bytes += stransfer->staging->buf->size;
+ r600_resource_reference(&stransfer->staging, NULL);
}
/* Heuristic for {upload, draw, upload, draw, ..}:
unsigned width0, unsigned height0,
unsigned width, unsigned height)
{
- struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
+ struct si_surface *surface = CALLOC_STRUCT(si_surface);
if (!surface)
return NULL;
!(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) ||
tex->buffer.b.b.target != PIPE_TEXTURE_2D ||
tex->buffer.b.b.last_level > 0 ||
- !tex->surface.dcc_size)
+ !tex->surface.dcc_size ||
+ sctx->screen->debug_flags & DBG(NO_DCC) ||
+ sctx->screen->debug_flags & DBG(NO_DCC_FB))
return;
+ assert(sctx->chip_class >= VI);
+
if (tex->dcc_offset)
return; /* already enabled */
union pipe_query_result result;
/* Read the results. */
- ctx->get_query_result(ctx, sctx->dcc_stats[i].ps_stats[2],
+ struct pipe_query *query = sctx->dcc_stats[i].ps_stats[2];
+ ctx->get_query_result(ctx, query,
true, &result);
- si_query_hw_reset_buffers(sctx,
- (struct si_query_hw*)
- sctx->dcc_stats[i].ps_stats[2]);
+ si_query_buffer_reset(sctx, &((struct si_query_hw*)query)->buffer);
/* Compute the approximate number of fullscreen draws. */
tex->ps_draw_ratio =
bool dedicated)
{
struct si_screen *sscreen = (struct si_screen*)screen;
- struct r600_memory_object *memobj = CALLOC_STRUCT(r600_memory_object);
+ struct si_memory_object *memobj = CALLOC_STRUCT(si_memory_object);
struct pb_buffer *buf = NULL;
uint32_t stride, offset;
return NULL;
buf = sscreen->ws->buffer_from_handle(sscreen->ws, whandle,
+ sscreen->info.max_alignment,
&stride, &offset);
if (!buf) {
free(memobj);
si_memobj_destroy(struct pipe_screen *screen,
struct pipe_memory_object *_memobj)
{
- struct r600_memory_object *memobj = (struct r600_memory_object *)_memobj;
+ struct si_memory_object *memobj = (struct si_memory_object *)_memobj;
pb_reference(&memobj->buf, NULL);
free(memobj);
uint64_t offset)
{
struct si_screen *sscreen = (struct si_screen*)screen;
- struct r600_memory_object *memobj = (struct r600_memory_object *)_memobj;
+ struct si_memory_object *memobj = (struct si_memory_object *)_memobj;
struct pipe_resource *tex =
si_texture_from_winsys_buffer(sscreen, templ, memobj->buf,
memobj->stride, offset,
- PIPE_HANDLE_USAGE_READ_WRITE,
+ PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE |
+ PIPE_HANDLE_USAGE_SHADER_WRITE,
memobj->b.dedicated);
if (!tex)
return NULL;
projects / mesa.git / blobdiff