*
**************************************************************************/
-/*
- * Authors:
- * Christian König <christian.koenig@amd.com>
- *
- */
-
#include "si_pipe.h"
#include "radeon/radeon_video.h"
#include "radeon/radeon_uvd.h"
#include "radeon/radeon_vce.h"
+#include "radeon/radeon_vcn_dec.h"
+#include "radeon/radeon_vcn_enc.h"
+#include "radeon/radeon_uvd_enc.h"
+#include "util/u_video.h"
/**
* creates an video buffer with an UVD compatible memory layout
{
struct si_context *ctx = (struct si_context *)pipe;
struct r600_texture *resources[VL_NUM_COMPONENTS] = {};
- struct radeon_surface *surfaces[VL_NUM_COMPONENTS] = {};
+ struct radeon_surf *surfaces[VL_NUM_COMPONENTS] = {};
struct pb_buffer **pbs[VL_NUM_COMPONENTS] = {};
const enum pipe_format *resource_formats;
- struct pipe_video_buffer template;
+ struct pipe_video_buffer vidtemplate;
struct pipe_resource templ;
unsigned i, array_size;
return NULL;
array_size = tmpl->interlaced ? 2 : 1;
- template = *tmpl;
- template.width = align(tmpl->width, VL_MACROBLOCK_WIDTH);
- template.height = align(tmpl->height / array_size, VL_MACROBLOCK_HEIGHT);
-
- vl_video_buffer_template(&templ, &template, resource_formats[0], 1, array_size, PIPE_USAGE_DEFAULT, 0);
- /* TODO: get tiling working */
- templ.bind = PIPE_BIND_LINEAR;
- resources[0] = (struct r600_texture *)
- pipe->screen->resource_create(pipe->screen, &templ);
- if (!resources[0])
- goto error;
-
- if (resource_formats[1] != PIPE_FORMAT_NONE) {
- vl_video_buffer_template(&templ, &template, resource_formats[1], 1, array_size, PIPE_USAGE_DEFAULT, 1);
- templ.bind = PIPE_BIND_LINEAR;
- resources[1] = (struct r600_texture *)
- pipe->screen->resource_create(pipe->screen, &templ);
- if (!resources[1])
- goto error;
- }
+ vidtemplate = *tmpl;
+ vidtemplate.width = align(tmpl->width, VL_MACROBLOCK_WIDTH);
+ vidtemplate.height = align(tmpl->height / array_size, VL_MACROBLOCK_HEIGHT);
- if (resource_formats[2] != PIPE_FORMAT_NONE) {
- vl_video_buffer_template(&templ, &template, resource_formats[2], 1, array_size, PIPE_USAGE_DEFAULT, 2);
- templ.bind = PIPE_BIND_LINEAR;
- resources[2] = (struct r600_texture *)
- pipe->screen->resource_create(pipe->screen, &templ);
- if (!resources[2])
- goto error;
+ assert(resource_formats[0] != PIPE_FORMAT_NONE);
+
+ for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
+ if (resource_formats[i] != PIPE_FORMAT_NONE) {
+ vl_video_buffer_template(&templ, &vidtemplate,
+ resource_formats[i], 1,
+ array_size, PIPE_USAGE_DEFAULT, i);
+ /* Set PIPE_BIND_SHARED to avoid reallocation in r600_texture_get_handle,
+ * which can't handle joined surfaces. */
+ /* TODO: get tiling working */
+ templ.bind = PIPE_BIND_LINEAR | PIPE_BIND_SHARED;
+ resources[i] = (struct r600_texture *)
+ pipe->screen->resource_create(pipe->screen, &templ);
+ if (!resources[i])
+ goto error;
+ }
}
for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
pbs[i] = &resources[i]->resource.buf;
}
- rvid_join_surfaces(ctx->b.ws, templ.bind, pbs, surfaces);
+ si_vid_join_surfaces(&ctx->b, pbs, surfaces);
for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
if (!resources[i])
continue;
- /* recreate the CS handle */
- resources[i]->resource.cs_buf = ctx->b.ws->buffer_get_cs_handle(
+ /* reset the address */
+ resources[i]->resource.gpu_address = ctx->b.ws->buffer_get_virtual_address(
resources[i]->resource.buf);
}
- template.height *= array_size;
- return vl_video_buffer_create_ex2(pipe, &template, (struct pipe_resource **)resources);
+ vidtemplate.height *= array_size;
+ return vl_video_buffer_create_ex2(pipe, &vidtemplate, (struct pipe_resource **)resources);
error:
for (i = 0; i < VL_NUM_COMPONENTS; ++i)
- pipe_resource_reference((struct pipe_resource **)&resources[i], NULL);
+ r600_texture_reference(&resources[i], NULL);
return NULL;
}
/* set the decoding target buffer offsets */
-static struct radeon_winsys_cs_handle* si_uvd_set_dtb(struct ruvd_msg *msg, struct vl_video_buffer *buf)
+static struct pb_buffer* si_uvd_set_dtb(struct ruvd_msg *msg, struct vl_video_buffer *buf)
{
+ struct si_screen *sscreen = (struct si_screen*)buf->base.context->screen;
struct r600_texture *luma = (struct r600_texture *)buf->resources[0];
struct r600_texture *chroma = (struct r600_texture *)buf->resources[1];
+ enum ruvd_surface_type type = (sscreen->info.chip_class >= GFX9) ?
+ RUVD_SURFACE_TYPE_GFX9 :
+ RUVD_SURFACE_TYPE_LEGACY;
msg->body.decode.dt_field_mode = buf->base.interlaced;
- ruvd_set_dt_surfaces(msg, &luma->surface, &chroma->surface);
+ si_uvd_set_dt_surfaces(msg, &luma->surface, (chroma) ? &chroma->surface : NULL, type);
- return luma->resource.cs_buf;
+ return luma->resource.buf;
}
/* get the radeon resources for VCE */
static void si_vce_get_buffer(struct pipe_resource *resource,
- struct radeon_winsys_cs_handle **handle,
- struct radeon_surface **surface)
+ struct pb_buffer **handle,
+ struct radeon_surf **surface)
{
struct r600_texture *res = (struct r600_texture *)resource;
if (handle)
- *handle = res->resource.cs_buf;
+ *handle = res->resource.buf;
if (surface)
*surface = &res->surface;
const struct pipe_video_codec *templ)
{
struct si_context *ctx = (struct si_context *)context;
+ bool vcn = (ctx->b.family == CHIP_RAVEN) ? true : false;
+
+ if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
+ if (vcn) {
+ radeon_create_encoder(context, templ, ctx->b.ws, si_vce_get_buffer);
+ } else {
+ if (u_reduce_video_profile(templ->profile) == PIPE_VIDEO_FORMAT_HEVC)
+ return radeon_uvd_create_encoder(context, templ, ctx->b.ws, si_vce_get_buffer);
+ else
+ return si_vce_create_encoder(context, templ, ctx->b.ws, si_vce_get_buffer);
+ }
+ }
- if (templ->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE)
- return rvce_create_encoder(context, templ, ctx->b.ws, si_vce_get_buffer);
-
- return ruvd_create_decoder(context, templ, si_uvd_set_dtb);
+ return (vcn) ? radeon_create_decoder(context, templ) :
+ si_common_uvd_create_decoder(context, templ, si_uvd_set_dtb);
}
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