radeonsi: extract TGSI memory/texture opcode handling into its own file

[mesa.git] / src / gallium / drivers / radeonsi / si_uvd.c

diff --git a/src/gallium/drivers/radeonsi/si_uvd.c b/src/gallium/drivers/radeonsi/si_uvd.c
index 9f25cd6b09a273e27c785c408595b5f7eeb5878b..53a7ce9402cabe2a8120c19ecf22827fec542725 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_uvd.c
+++ b/src/gallium/drivers/radeonsi/si_uvd.c
@@ -44,7 +44,7 @@ struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
 {
        struct si_context *ctx = (struct si_context *)pipe;
        struct r600_texture *resources[VL_NUM_COMPONENTS] = {};
-       struct radeon_surface *surfaces[VL_NUM_COMPONENTS] = {};
+       struct radeon_surf *surfaces[VL_NUM_COMPONENTS] = {};
        struct pb_buffer **pbs[VL_NUM_COMPONENTS] = {};
        const enum pipe_format *resource_formats;
        struct pipe_video_buffer template;
@@ -97,14 +97,14 @@ struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
                pbs[i] = &resources[i]->resource.buf;
        }
 
-       rvid_join_surfaces(ctx->b.ws, templ.bind, pbs, surfaces);
+       rvid_join_surfaces(&ctx->b, pbs, surfaces);
 
        for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
                if (!resources[i])
                        continue;
 
-               /* recreate the CS handle */
-               resources[i]->resource.cs_buf = ctx->b.ws->buffer_get_cs_handle(
+               /* reset the address */
+               resources[i]->resource.gpu_address = ctx->b.ws->buffer_get_virtual_address(
                        resources[i]->resource.buf);
        }
 
@@ -113,33 +113,37 @@ struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
 
 error:
        for (i = 0; i < VL_NUM_COMPONENTS; ++i)
-               pipe_resource_reference((struct pipe_resource **)&resources[i], NULL);
+               r600_texture_reference(&resources[i], NULL);
 
        return NULL;
 }
 
 /* set the decoding target buffer offsets */
-static struct radeon_winsys_cs_handle* si_uvd_set_dtb(struct ruvd_msg *msg, struct vl_video_buffer *buf)
+static struct pb_buffer* si_uvd_set_dtb(struct ruvd_msg *msg, struct vl_video_buffer *buf)
 {
+       struct si_screen *sscreen = (struct si_screen*)buf->base.context->screen;
        struct r600_texture *luma = (struct r600_texture *)buf->resources[0];
        struct r600_texture *chroma = (struct r600_texture *)buf->resources[1];
+       enum ruvd_surface_type type =  (sscreen->b.chip_class >= GFX9) ?
+                                       RUVD_SURFACE_TYPE_GFX9 :
+                                       RUVD_SURFACE_TYPE_LEGACY;
 
        msg->body.decode.dt_field_mode = buf->base.interlaced;
 
-       ruvd_set_dt_surfaces(msg, &luma->surface, &chroma->surface);
+       ruvd_set_dt_surfaces(msg, &luma->surface, &chroma->surface, type);
 
-       return luma->resource.cs_buf;
+       return luma->resource.buf;
 }
 
 /* get the radeon resources for VCE */
 static void si_vce_get_buffer(struct pipe_resource *resource,
-                             struct radeon_winsys_cs_handle **handle,
-                             struct radeon_surface **surface)
+                             struct pb_buffer **handle,
+                             struct radeon_surf **surface)
 {
        struct r600_texture *res = (struct r600_texture *)resource;
 
        if (handle)
-               *handle = res->resource.cs_buf;
+               *handle = res->resource.buf;
 
        if (surface)
                *surface = &res->surface;