r600g,radeonsi: don't skip the context flush if a fence should be returned
[mesa.git] / src / gallium / drivers / radeonsi / sid.h
index 86394075cf0af031fc61fea261e7e337aa83ef1d..2bd2cb4b1e4ac13508f65f210659a5193392e82b 100644 (file)
 #define                WAIT_REG_MEM_EQUAL              3
 #define PKT3_MEM_WRITE                         0x3D /* not on CIK */
 #define PKT3_INDIRECT_BUFFER                   0x32
+#define PKT3_COPY_DATA                        0x40
+#define                COPY_DATA_SRC_SEL(x)            ((x) & 0xf)
+#define                        COPY_DATA_REG           0
+#define                        COPY_DATA_MEM           1
+#define                COPY_DATA_DST_SEL(x)            (((x) & 0xf) << 8)
+#define                COPY_DATA_WR_CONFIRM            (1 << 20)
 #define PKT3_SURFACE_SYNC                      0x43 /* deprecated on CIK, use ACQUIRE_MEM */
 #define PKT3_ME_INITIALIZE                     0x44 /* not on CIK */
 #define PKT3_COND_WRITE                        0x45
 #define PKT3_PREDICATE(x)               (((x) >> 0) & 0x1)
 #define PKT3_SHADER_TYPE_S(x)           (((x) & 0x1) << 1)
 #define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) | PKT_COUNT_S(count))
-#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate))
+#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
 
 #define PKT3_CP_DMA                                    0x41
 /* 1. header
 #define     V_02803C_X_ADDR_SURF_P8_32X32_16X16                     0x0C
 #define     V_02803C_X_ADDR_SURF_P8_32X32_16X32                     0x0D
 #define     V_02803C_X_ADDR_SURF_P8_32X64_32X32                     0x0E
+#define     V_02803C_X_ADDR_SURF_P16_32X32_8X16                     0x10
+#define     V_02803C_X_ADDR_SURF_P16_32X32_16X16                    0x11
 #define   S_02803C_BANK_WIDTH(x)                                      (((x) & 0x03) << 13)
 #define   G_02803C_BANK_WIDTH(x)                                      (((x) >> 13) & 0x03)
 #define   C_02803C_BANK_WIDTH                                         0xFFFF9FFF
 #define     V_028350_RASTER_CONFIG_PKR_YSEL_1                       0x01
 #define     V_028350_RASTER_CONFIG_PKR_YSEL_2                       0x02
 #define     V_028350_RASTER_CONFIG_PKR_YSEL_3                       0x03
+#define   S_028350_PKR_XSEL2(x)                                       (((x) & 0x03) << 14)
+#define   G_028350_PKR_XSEL2(x)                                       (((x) >> 14) & 0x03)
+#define   C_028350_PKR_XSEL2                                          0xFFFF3FFF
+#define     V_028350_RASTER_CONFIG_PKR_XSEL2_0                      0x00
+#define     V_028350_RASTER_CONFIG_PKR_XSEL2_1                      0x01
+#define     V_028350_RASTER_CONFIG_PKR_XSEL2_2                      0x02
+#define     V_028350_RASTER_CONFIG_PKR_XSEL2_3                      0x03
 #define   S_028350_SC_MAP(x)                                          (((x) & 0x03) << 16)
 #define   G_028350_SC_MAP(x)                                          (((x) >> 16) & 0x03)
 #define   C_028350_SC_MAP                                             0xFFFCFFFF
 #define   S_028A6C_OUTPRIM_TYPE(x)                                    (((x) & 0x3F) << 0)
 #define   G_028A6C_OUTPRIM_TYPE(x)                                    (((x) >> 0) & 0x3F)
 #define   C_028A6C_OUTPRIM_TYPE                                       0xFFFFFFC0
+#define     V_028A6C_OUTPRIM_TYPE_POINTLIST            0
+#define     V_028A6C_OUTPRIM_TYPE_LINESTRIP            1
+#define     V_028A6C_OUTPRIM_TYPE_TRISTRIP             2
 #define   S_028A6C_OUTPRIM_TYPE_1(x)                                  (((x) & 0x3F) << 8)
 #define   G_028A6C_OUTPRIM_TYPE_1(x)                                  (((x) >> 8) & 0x3F)
 #define   C_028A6C_OUTPRIM_TYPE_1                                     0xFFFFC0FF
 #define   S_028BDC_DX10_DIAMOND_TEST_ENA(x)                           (((x) & 0x1) << 12)
 #define   G_028BDC_DX10_DIAMOND_TEST_ENA(x)                           (((x) >> 12) & 0x1)
 #define   C_028BDC_DX10_DIAMOND_TEST_ENA                              0xFFFFEFFF
-#define R_028BE0_PA_SC_AA_CONFIG                                        0x028BE0
-#define   S_028BE0_MSAA_NUM_SAMPLES(x)                                (((x) & 0x07) << 0)
-#define   G_028BE0_MSAA_NUM_SAMPLES(x)                                (((x) >> 0) & 0x07)
-#define   C_028BE0_MSAA_NUM_SAMPLES                                   0xFFFFFFF8
-#define   S_028BE0_AA_MASK_CENTROID_DTMN(x)                           (((x) & 0x1) << 4)
-#define   G_028BE0_AA_MASK_CENTROID_DTMN(x)                           (((x) >> 4) & 0x1)
-#define   C_028BE0_AA_MASK_CENTROID_DTMN                              0xFFFFFFEF
-#define   S_028BE0_MAX_SAMPLE_DIST(x)                                 (((x) & 0x0F) << 13)
-#define   G_028BE0_MAX_SAMPLE_DIST(x)                                 (((x) >> 13) & 0x0F)
-#define   C_028BE0_MAX_SAMPLE_DIST                                    0xFFFE1FFF
-#define   S_028BE0_MSAA_EXPOSED_SAMPLES(x)                            (((x) & 0x07) << 20)
-#define   G_028BE0_MSAA_EXPOSED_SAMPLES(x)                            (((x) >> 20) & 0x07)
-#define   C_028BE0_MSAA_EXPOSED_SAMPLES                               0xFF8FFFFF
-#define   S_028BE0_DETAIL_TO_EXPOSED_MODE(x)                          (((x) & 0x03) << 24)
-#define   G_028BE0_DETAIL_TO_EXPOSED_MODE(x)                          (((x) >> 24) & 0x03)
-#define   C_028BE0_DETAIL_TO_EXPOSED_MODE                             0xFCFFFFFF
 #define R_028BE4_PA_SU_VTX_CNTL                                         0x028BE4
 #define   S_028BE4_PIX_CENTER(x)                                      (((x) & 0x1) << 0)
 #define   G_028BE4_PIX_CENTER(x)                                      (((x) >> 0) & 0x1)
 #define   S_028C74_FMASK_TILE_MODE_INDEX(x)                           (((x) & 0x1F) << 5)
 #define   G_028C74_FMASK_TILE_MODE_INDEX(x)                           (((x) >> 5) & 0x1F)
 #define   C_028C74_FMASK_TILE_MODE_INDEX                              0xFFFFFC1F
+#define   S_028C74_FMASK_BANK_HEIGHT(x)                                      (((x) & 0x3) << 10) /* SI errata */
 #define   S_028C74_NUM_SAMPLES(x)                                     (((x) & 0x07) << 12)
 #define   G_028C74_NUM_SAMPLES(x)                                     (((x) >> 12) & 0x07)
 #define   C_028C74_NUM_SAMPLES                                        0xFFFF8FFF
 #define R_028E30_CB_COLOR7_CLEAR_WORD0                                  0x028E30
 #define R_028E34_CB_COLOR7_CLEAR_WORD1                                  0x028E34
 
+/* SI async DMA packets */
+#define SI_DMA_PACKET(cmd, sub_cmd, n) ((((cmd) & 0xF) << 28) |    \
+                                       (((sub_cmd) & 0xFF) << 20) |\
+                                       (((n) & 0xFFFFF) << 0))
+/* SI async DMA Packet types */
+#define    SI_DMA_PACKET_WRITE                     0x2
+#define    SI_DMA_PACKET_COPY                      0x3
+#define    SI_DMA_COPY_MAX_SIZE                    0xfffe0
+#define    SI_DMA_COPY_MAX_SIZE_DW                 0xffff8
+#define    SI_DMA_COPY_DWORD_ALIGNED               0x00
+#define    SI_DMA_COPY_BYTE_ALIGNED                0x40
+#define    SI_DMA_COPY_TILED                       0x8
+#define    SI_DMA_PACKET_INDIRECT_BUFFER           0x4
+#define    SI_DMA_PACKET_SEMAPHORE                 0x5
+#define    SI_DMA_PACKET_FENCE                     0x6
+#define    SI_DMA_PACKET_TRAP                      0x7
+#define    SI_DMA_PACKET_SRBM_WRITE                0x9
+#define    SI_DMA_PACKET_CONSTANT_FILL             0xd
+#define    SI_DMA_PACKET_NOP                       0xf
+
 #endif /* _SID_H */