radeonsi: inline util_blitter_copy_texture

[mesa.git] / src / gallium / drivers / radeonsi / sid.h

diff --git a/src/gallium/drivers/radeonsi/sid.h b/src/gallium/drivers/radeonsi/sid.h
index c6688b37abc117645dffa431be4bbb8f92d44826..aab39fcfc877a1e478d9dee81e1c6c0422e9afbd 100644 (file)
--- a/src/gallium/drivers/radeonsi/sid.h
+++ b/src/gallium/drivers/radeonsi/sid.h
@@ -103,6 +103,12 @@
 #define                WAIT_REG_MEM_EQUAL              3
 #define PKT3_MEM_WRITE                         0x3D /* not on CIK */
 #define PKT3_INDIRECT_BUFFER                   0x32
+#define PKT3_COPY_DATA                        0x40
+#define                COPY_DATA_SRC_SEL(x)            ((x) & 0xf)
+#define                        COPY_DATA_REG           0
+#define                        COPY_DATA_MEM           1
+#define                COPY_DATA_DST_SEL(x)            (((x) & 0xf) << 8)
+#define                COPY_DATA_WR_CONFIRM            (1 << 20)
 #define PKT3_SURFACE_SYNC                      0x43 /* deprecated on CIK, use ACQUIRE_MEM */
 #define PKT3_ME_INITIALIZE                     0x44 /* not on CIK */
 #define PKT3_COND_WRITE                        0x45
@@ -5397,6 +5403,8 @@
 #define     V_02803C_X_ADDR_SURF_P8_32X32_16X16                     0x0C
 #define     V_02803C_X_ADDR_SURF_P8_32X32_16X32                     0x0D
 #define     V_02803C_X_ADDR_SURF_P8_32X64_32X32                     0x0E
+#define     V_02803C_X_ADDR_SURF_P16_32X32_8X16                     0x10
+#define     V_02803C_X_ADDR_SURF_P16_32X32_16X16                    0x11
 #define   S_02803C_BANK_WIDTH(x)                                      (((x) & 0x03) << 13)
 #define   G_02803C_BANK_WIDTH(x)                                      (((x) >> 13) & 0x03)
 #define   C_02803C_BANK_WIDTH                                         0xFFFF9FFF
@@ -5725,6 +5733,13 @@
 #define     V_028350_RASTER_CONFIG_PKR_YSEL_1                       0x01
 #define     V_028350_RASTER_CONFIG_PKR_YSEL_2                       0x02
 #define     V_028350_RASTER_CONFIG_PKR_YSEL_3                       0x03
+#define   S_028350_PKR_XSEL2(x)                                       (((x) & 0x03) << 14)
+#define   G_028350_PKR_XSEL2(x)                                       (((x) >> 14) & 0x03)
+#define   C_028350_PKR_XSEL2                                          0xFFFF3FFF
+#define     V_028350_RASTER_CONFIG_PKR_XSEL2_0                      0x00
+#define     V_028350_RASTER_CONFIG_PKR_XSEL2_1                      0x01
+#define     V_028350_RASTER_CONFIG_PKR_XSEL2_2                      0x02
+#define     V_028350_RASTER_CONFIG_PKR_XSEL2_3                      0x03
 #define   S_028350_SC_MAP(x)                                          (((x) & 0x03) << 16)
 #define   G_028350_SC_MAP(x)                                          (((x) >> 16) & 0x03)
 #define   C_028350_SC_MAP                                             0xFFFCFFFF