ilo: remove ilo_cbuf_state::count

[mesa.git] / src / gallium / drivers / softpipe / sp_tex_tile_cache.h

diff --git a/src/gallium/drivers/softpipe/sp_tex_tile_cache.h b/src/gallium/drivers/softpipe/sp_tex_tile_cache.h
index 12ae7ba12d62a91928266913ff6a94a14bc81214..213d0ecead04c1d0ba1b06785fabffac258c7294 100644 (file)
--- a/src/gallium/drivers/softpipe/sp_tex_tile_cache.h
+++ b/src/gallium/drivers/softpipe/sp_tex_tile_cache.h
@@ -30,6 +30,7 @@
 
 
 #include "pipe/p_compiler.h"
+#include "sp_limits.h"
 
 
 struct softpipe_context;
@@ -39,22 +40,26 @@ struct softpipe_tex_tile_cache;
 /**
  * Cache tile size (width and height). This needs to be a power of two.
  */
-#define TILE_SIZE 64
+#define TEX_TILE_SIZE_LOG2 5
+#define TEX_TILE_SIZE (1 << TEX_TILE_SIZE_LOG2)
 
 
-/* If we need to support > 4096, just expand this to be a 64 bit
- * union, or consider tiling in Z as well.
+#define TEX_ADDR_BITS (SP_MAX_TEXTURE_2D_LEVELS - 1 - TEX_TILE_SIZE_LOG2)
+#define TEX_Z_BITS (SP_MAX_TEXTURE_2D_LEVELS - 1)
+
+/**
+ * Texture tile address as a union for fast compares.
  */
 union tex_tile_address {
    struct {
-      unsigned x:6;             /* 4096 / TILE_SIZE */
-      unsigned y:6;             /* 4096 / TILE_SIZE */
-      unsigned z:12;            /* 4096 -- z not tiled */
+      unsigned x:TEX_ADDR_BITS;  /* 16K / TILE_SIZE */
+      unsigned y:TEX_ADDR_BITS;  /* 16K / TILE_SIZE */
+      unsigned z:TEX_Z_BITS;     /* 16K -- z not tiled */
       unsigned face:3;
       unsigned level:4;
       unsigned invalid:1;
    } bits;
-   unsigned value;
+   uint64_t value;
 };
 
 
@@ -62,11 +67,19 @@ struct softpipe_tex_cached_tile
 {
    union tex_tile_address addr;
    union {
-      float color[TILE_SIZE][TILE_SIZE][4];
+      float color[TEX_TILE_SIZE][TEX_TILE_SIZE][4];
+      unsigned int colorui[TEX_TILE_SIZE][TEX_TILE_SIZE][4];
+      int colori[TEX_TILE_SIZE][TEX_TILE_SIZE][4];
    } data;
 };
 
-#define NUM_ENTRIES 50
+/*
+ * The number of cache entries.
+ * Should not be decreased to lower than 16, and even that
+ * seems too low to avoid cache thrashing in some cases (because
+ * the cache is direct mapped, see tex_cache_pos() function).
+ */
+#define NUM_TEX_TILE_ENTRIES 16
 
 struct softpipe_tex_tile_cache
 {
@@ -74,10 +87,10 @@ struct softpipe_tex_tile_cache
    struct pipe_transfer *transfer;
    void *transfer_map;
 
-   struct pipe_texture *texture;  /**< if caching a texture */
+   struct pipe_resource *texture;  /**< if caching a texture */
    unsigned timestamp;
 
-   struct softpipe_tex_cached_tile entries[NUM_ENTRIES];
+   struct softpipe_tex_cached_tile entries[NUM_TEX_TILE_ENTRIES];
 
    struct pipe_transfer *tex_trans;
    void *tex_trans_map;
@@ -87,7 +100,7 @@ struct softpipe_tex_tile_cache
    unsigned swizzle_g;
    unsigned swizzle_b;
    unsigned swizzle_a;
-   unsigned format;
+   enum pipe_format format;
 
    struct softpipe_tex_cached_tile *last_tile;  /**< most recently retrieved tile */
 };
@@ -99,13 +112,6 @@ sp_create_tex_tile_cache( struct pipe_context *pipe );
 extern void
 sp_destroy_tex_tile_cache(struct softpipe_tex_tile_cache *tc);
 
-
-extern void
-sp_tex_tile_cache_map_transfers(struct softpipe_tex_tile_cache *tc);
-
-extern void
-sp_tex_tile_cache_unmap_transfers(struct softpipe_tex_tile_cache *tc);
-
 extern void
 sp_tex_tile_cache_set_sampler_view(struct softpipe_tex_tile_cache *tc,
                                    struct pipe_sampler_view *view);
@@ -120,24 +126,24 @@ sp_flush_tex_tile_cache(struct softpipe_tex_tile_cache *tc);
 
 extern const struct softpipe_tex_cached_tile *
 sp_find_cached_tile_tex(struct softpipe_tex_tile_cache *tc, 
-                         union tex_tile_address addr );
+                        union tex_tile_address addr );
 
 static INLINE union tex_tile_address
 tex_tile_address( unsigned x,
-                 unsigned y,
-                 unsigned z,
-                 unsigned face,
-                 unsigned level )
+                  unsigned y,
+                  unsigned z,
+                  unsigned face,
+                  unsigned level )
 {
    union tex_tile_address addr;
 
    addr.value = 0;
-   addr.bits.x = x / TILE_SIZE;
-   addr.bits.y = y / TILE_SIZE;
+   addr.bits.x = x / TEX_TILE_SIZE;
+   addr.bits.y = y / TEX_TILE_SIZE;
    addr.bits.z = z;
    addr.bits.face = face;
    addr.bits.level = level;
-      
+
    return addr;
 }
 
@@ -145,7 +151,7 @@ tex_tile_address( unsigned x,
  */
 static INLINE const struct softpipe_tex_cached_tile *
 sp_get_cached_tile_tex(struct softpipe_tex_tile_cache *tc, 
-                         union tex_tile_address addr )
+                       union tex_tile_address addr )
 {
    if (tc->last_tile->addr.value == addr.value)
       return tc->last_tile;
@@ -154,8 +160,5 @@ sp_get_cached_tile_tex(struct softpipe_tex_tile_cache *tc,
 }
 
 
-
-
-
 #endif /* SP_TEX_TILE_CACHE_H */