define_depth_stencil_state_object(struct svga_context *svga,
struct svga_depth_stencil_state *ds)
{
- unsigned try;
-
assert(svga_have_vgpu10(svga));
ds->id = util_bitmask_add(svga->ds_object_id_bm);
STATIC_ASSERT(SVGA3D_COMPARISON_LESS == SVGA3D_CMP_LESS);
STATIC_ASSERT(SVGA3D_COMPARISON_NOT_EQUAL == SVGA3D_CMP_NOTEQUAL);
- /* Loop in case command buffer is full and we need to flush and retry */
- for (try = 0; try < 2; try++) {
- enum pipe_error ret;
-
- /* Note: we use the ds->stencil[0].enabled value for both the front
- * and back-face enables. If single-side stencil is used, we'll have
- * set the back state the same as the front state.
- */
- ret = SVGA3D_vgpu10_DefineDepthStencilState(svga->swc,
- ds->id,
- /* depth/Z */
- ds->zenable,
- ds->zwriteenable,
- ds->zfunc,
- /* Stencil */
- ds->stencil[0].enabled, /*f|b*/
- ds->stencil[0].enabled, /*f*/
- ds->stencil[0].enabled, /*b*/
- ds->stencil_mask,
- ds->stencil_writemask,
- /* front stencil */
- ds->stencil[0].fail,
- ds->stencil[0].zfail,
- ds->stencil[0].pass,
- ds->stencil[0].func,
- /* back stencil */
- ds->stencil[1].fail,
- ds->stencil[1].zfail,
- ds->stencil[1].pass,
- ds->stencil[1].func);
- if (ret == PIPE_OK)
- return;
- svga_context_flush(svga, NULL);
- }
+ /* Note: we use the ds->stencil[0].enabled value for both the front
+ * and back-face enables. If single-side stencil is used, we'll have
+ * set the back state the same as the front state.
+ */
+ SVGA_RETRY(svga, SVGA3D_vgpu10_DefineDepthStencilState
+ (svga->swc,
+ ds->id,
+ /* depth/Z */
+ ds->zenable,
+ ds->zwriteenable,
+ ds->zfunc,
+ /* Stencil */
+ ds->stencil[0].enabled, /*f|b*/
+ ds->stencil[0].enabled, /*f*/
+ ds->stencil[0].enabled, /*b*/
+ ds->stencil_mask,
+ ds->stencil_writemask,
+ /* front stencil */
+ ds->stencil[0].fail,
+ ds->stencil[0].zfail,
+ ds->stencil[0].pass,
+ ds->stencil[0].func,
+ /* back stencil */
+ ds->stencil[1].fail,
+ ds->stencil[1].zfail,
+ ds->stencil[1].pass,
+ ds->stencil[1].func));
}
ds->stencil_mask = templ->stencil[1].valuemask & 0xff;
ds->stencil_writemask = templ->stencil[1].writemask & 0xff;
+
+ if (templ->stencil[1].valuemask != templ->stencil[0].valuemask) {
+ pipe_debug_message(&svga->debug.callback, CONFORMANCE,
+ "two-sided stencil mask not supported "
+ "(front=0x%x, back=0x%x)",
+ templ->stencil[0].valuemask,
+ templ->stencil[1].valuemask);
+ }
+ if (templ->stencil[1].writemask != templ->stencil[0].writemask) {
+ pipe_debug_message(&svga->debug.callback, CONFORMANCE,
+ "two-sided stencil writemask not supported "
+ "(front=0x%x, back=0x%x)",
+ templ->stencil[0].writemask,
+ templ->stencil[1].writemask);
+ }
}
else {
/* back face state is same as front-face state */
(struct svga_depth_stencil_state *) depth_stencil;
if (svga_have_vgpu10(svga)) {
- enum pipe_error ret;
-
svga_hwtnl_flush_retry(svga);
assert(ds->id != SVGA3D_INVALID_ID);
- ret = SVGA3D_vgpu10_DestroyDepthStencilState(svga->swc, ds->id);
- if (ret != PIPE_OK) {
- svga_context_flush(svga, NULL);
- ret = SVGA3D_vgpu10_DestroyDepthStencilState(svga->swc, ds->id);
- assert(ret == PIPE_OK);
- }
+ SVGA_RETRY(svga, SVGA3D_vgpu10_DestroyDepthStencilState(svga->swc,
+ ds->id));
if (ds->id == svga->state.hw_draw.depth_stencil_id)
svga->state.hw_draw.depth_stencil_id = SVGA3D_INVALID_ID;
}
+static void
+svga_set_min_samples(struct pipe_context *pipe, unsigned min_samples)
+{
+ /* This specifies the minimum number of times the fragment shader
+ * must run when doing per-sample shading for a MSAA render target.
+ * For our SVGA3D device, the FS is automatically run in per-sample
+ * mode if it uses the sample ID or sample position registers.
+ */
+}
+
+
void
svga_init_depth_stencil_functions(struct svga_context *svga)
{
svga->pipe.set_stencil_ref = svga_set_stencil_ref;
svga->pipe.set_sample_mask = svga_set_sample_mask;
+ svga->pipe.set_min_samples = svga_set_min_samples;
}