**********************************************************/
#include "git_sha1.h" /* For MESA_GIT_SHA1 */
-#include "util/u_format.h"
+#include "util/format/u_format.h"
#include "util/u_memory.h"
#include "util/u_inlines.h"
+#include "util/u_screen.h"
#include "util/u_string.h"
#include "util/u_math.h"
#include "svga_public.h"
#include "svga_context.h"
#include "svga_format.h"
-#include "svga_msg.h"
#include "svga_screen.h"
#include "svga_tgsi.h"
#include "svga_resource_texture.h"
*/
build = "build: DEBUG;";
mutex = "mutex: " PIPE_ATOMIC ";";
-#elif defined(VMX86_STATS)
- build = "build: OPT;";
#else
build = "build: RELEASE;";
#endif
-#ifdef HAVE_LLVM
+#ifdef LLVM_AVAILABLE
llvm = "LLVM;";
#endif
- util_snprintf(name, sizeof(name), "SVGA3D; %s %s %s", build, mutex, llvm);
+ snprintf(name, sizeof(name), "SVGA3D; %s %s %s", build, mutex, llvm);
return name;
}
/** Helper for querying float-valued device cap */
static float
-get_float_cap(struct svga_winsys_screen *sws, unsigned cap, float defaultVal)
+get_float_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap,
+ float defaultVal)
{
SVGA3dDevCapResult result;
if (sws->get_cap(sws, cap, &result))
/** Helper for querying uint-valued device cap */
static unsigned
-get_uint_cap(struct svga_winsys_screen *sws, unsigned cap, unsigned defaultVal)
+get_uint_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap,
+ unsigned defaultVal)
{
SVGA3dDevCapResult result;
if (sws->get_cap(sws, cap, &result))
/** Helper for querying boolean-valued device cap */
static boolean
-get_bool_cap(struct svga_winsys_screen *sws, unsigned cap, boolean defaultVal)
+get_bool_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap,
+ boolean defaultVal)
{
SVGA3dDevCapResult result;
if (sws->get_cap(sws, cap, &result))
case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
return 15.0;
- case PIPE_CAPF_GUARD_BAND_LEFT:
- case PIPE_CAPF_GUARD_BAND_TOP:
- case PIPE_CAPF_GUARD_BAND_RIGHT:
- case PIPE_CAPF_GUARD_BAND_BOTTOM:
- return 0.0;
+ case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
+ /* fall-through */
+ case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
+ /* fall-through */
+ case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
+ return 0.0f;
+
}
debug_printf("Unexpected PIPE_CAPF_ query %u\n", param);
case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
return 1;
- case PIPE_CAP_TWO_SIDED_STENCIL:
- return 1;
case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
/*
* "In virtually every OpenGL implementation and hardware,
return 0;
case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
return sws->have_vgpu10;
- case PIPE_CAP_TEXTURE_SHADOW_MAP:
- return 1;
case PIPE_CAP_TEXTURE_SWIZZLE:
return 1;
case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
return 0;
case PIPE_CAP_USER_VERTEX_BUFFERS:
return 0;
- case PIPE_CAP_USER_CONSTANT_BUFFERS:
- return 1;
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
return 256;
- case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
+ case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
{
- unsigned levels = SVGA_MAX_TEXTURE_LEVELS;
+ unsigned size = 1 << (SVGA_MAX_TEXTURE_LEVELS - 1);
if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH, &result))
- levels = MIN2(util_logbase2(result.u) + 1, levels);
+ size = MIN2(result.u, size);
else
- levels = 12 /* 2048x2048 */;
+ size = 2048;
if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT, &result))
- levels = MIN2(util_logbase2(result.u) + 1, levels);
+ size = MIN2(result.u, size);
else
- levels = 12 /* 2048x2048 */;
- return levels;
+ size = 2048;
+ return size;
}
case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
* No mechanism to query the host, and at least limited to 2048x2048 on
* certain hardware.
*/
- return MIN2(screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_LEVELS),
+ return MIN2(util_last_bit(screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_SIZE)),
12 /* 2048x2048 */);
case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
- return sws->have_vgpu10 ? SVGA3D_MAX_SURFACE_ARRAYSIZE : 0;
+ return sws->have_sm5 ? SVGA3D_SM5_MAX_SURFACE_ARRAYSIZE :
+ (sws->have_vgpu10 ? SVGA3D_SM4_MAX_SURFACE_ARRAYSIZE : 0);
case PIPE_CAP_BLEND_EQUATION_SEPARATE: /* req. for GL 1.5 */
return 1;
case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
return 1; /* The color outputs of vertex shaders are not clamped */
case PIPE_CAP_VERTEX_COLOR_CLAMPED:
- return 0; /* The driver can't clamp vertex colors */
+ return sws->have_vgpu10;
case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
return 0; /* The driver can't clamp fragment colors */
return 1; /* expected for GL_ARB_framebuffer_object */
case PIPE_CAP_GLSL_FEATURE_LEVEL:
- return sws->have_vgpu10 ? 330 : 120;
+ if (sws->have_sm5) {
+ return 410;
+ } else if (sws->have_vgpu10) {
+ return 330;
+ } else {
+ return 120;
+ }
+
+ case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
+ return sws->have_sm5 ? 410 : (sws->have_vgpu10 ? 330 : 120);
case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
+ case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
return 0;
- case PIPE_CAP_SM3:
+ case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
+ case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
+ case PIPE_CAP_VERTEX_SHADER_SATURATE:
return 1;
case PIPE_CAP_DEPTH_CLIP_DISABLE:
case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
return sws->have_vgpu10 ? 4 : 0;
case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
- return sws->have_vgpu10 ? SVGA3D_MAX_STREAMOUT_DECLS : 0;
+ return sws->have_sm5 ? SVGA3D_MAX_STREAMOUT_DECLS :
+ (sws->have_vgpu10 ? SVGA3D_MAX_DX10_STREAMOUT_DECLS : 0);
case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
+ return sws->have_sm5;
case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
- return 0;
+ return sws->have_sm5;
case PIPE_CAP_TEXTURE_MULTISAMPLE:
return svgascreen->ms_samples ? 1 : 0;
case PIPE_CAP_NATIVE_FENCE_FD:
return sws->have_fence_fd;
- /* Unsupported features */
case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
+ return 1;
+
+ case PIPE_CAP_CUBE_MAP_ARRAY:
+ case PIPE_CAP_INDEP_BLEND_FUNC:
+ case PIPE_CAP_SAMPLE_SHADING:
+ case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
+ case PIPE_CAP_TEXTURE_QUERY_LOD:
+ return sws->have_sm4_1;
+
+ case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
+ /* SM4_1 supports only single-channel textures where as SM5 supports
+ * all four channel textures */
+ return sws->have_sm5 ? 4 :
+ (sws->have_sm4_1 ? 1 : 0);
+ case PIPE_CAP_DRAW_INDIRECT:
+ return sws->have_sm5;
+ case PIPE_CAP_MAX_VERTEX_STREAMS:
+ return sws->have_sm5 ? 4 : 0;
+ case PIPE_CAP_COMPUTE:
+ return 0;
+ case PIPE_CAP_MAX_VARYINGS:
+ return sws->have_vgpu10 ? VGPU10_MAX_FS_INPUTS : 10;
+ case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
+ return sws->have_coherent;
+
+ /* Unsupported features */
case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
+ case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
case PIPE_CAP_SHADER_STENCIL_EXPORT:
case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
- case PIPE_CAP_INDEP_BLEND_FUNC:
case PIPE_CAP_TEXTURE_BARRIER:
- case PIPE_CAP_MAX_VERTEX_STREAMS:
case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
- case PIPE_CAP_COMPUTE:
case PIPE_CAP_START_INSTANCE:
- case PIPE_CAP_CUBE_MAP_ARRAY:
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
- case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
case PIPE_CAP_TEXTURE_GATHER_SM5:
- case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
- case PIPE_CAP_TEXTURE_QUERY_LOD:
- case PIPE_CAP_SAMPLE_SHADING:
case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
- case PIPE_CAP_DRAW_INDIRECT:
case PIPE_CAP_MULTI_DRAW_INDIRECT:
case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
case PIPE_CAP_PCI_DEVICE:
case PIPE_CAP_PCI_FUNCTION:
case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
+ case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
+ case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
+ case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
+ case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
+ case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
+ case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
+ case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
return 0;
case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
return 64;
case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
return 2048;
case PIPE_CAP_MAX_VIEWPORTS:
- return 1;
+ assert((!sws->have_vgpu10 && svgascreen->max_viewports == 1) ||
+ (sws->have_vgpu10 &&
+ svgascreen->max_viewports == SVGA3D_DX_MAX_VIEWPORTS));
+ return svgascreen->max_viewports;
case PIPE_CAP_ENDIANNESS:
return PIPE_ENDIAN_LITTLE;
return sws->have_vgpu10;
case PIPE_CAP_CLEAR_TEXTURE:
return sws->have_vgpu10;
+ case PIPE_CAP_DOUBLES:
+ return sws->have_sm5;
case PIPE_CAP_UMA:
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
- case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
case PIPE_CAP_DEPTH_BOUNDS_TEST:
case PIPE_CAP_TGSI_TXQS:
- case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
case PIPE_CAP_SHAREABLE_SHADERS:
case PIPE_CAP_DRAW_PARAMETERS:
case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
- case PIPE_CAP_TGSI_FS_FBFETCH:
+ case PIPE_CAP_FBFETCH:
case PIPE_CAP_TGSI_MUL_ZERO_WINS:
- case PIPE_CAP_DOUBLES:
case PIPE_CAP_INT64:
case PIPE_CAP_INT64_DIVMOD:
case PIPE_CAP_TGSI_TEX_TXF_LZ:
case PIPE_CAP_BINDLESS_TEXTURE:
case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
case PIPE_CAP_QUERY_SO_OVERFLOW:
+ case PIPE_CAP_MEMOBJ:
+ case PIPE_CAP_LOAD_CONSTBUF:
+ case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
+ case PIPE_CAP_TILE_RASTER_ORDER:
+ case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
+ case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
+ case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
+ case PIPE_CAP_CONTEXT_PRIORITY_MASK:
+ case PIPE_CAP_FENCE_SIGNAL:
+ case PIPE_CAP_CONSTBUF0_FLAGS:
+ case PIPE_CAP_PACKED_UNIFORMS:
+ case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
return 0;
+ case PIPE_CAP_TGSI_DIV:
+ return 1;
+ case PIPE_CAP_MAX_GS_INVOCATIONS:
+ return 32;
+ case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
+ return 1 << 27;
+ /* Verify this once protocol is finalized. Setting it to minimum value. */
+ case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
+ return sws->have_sm5 ? 30 : 0;
+ default:
+ return u_pipe_screen_get_param_defaults(screen, param);
}
-
- debug_printf("Unexpected PIPE_CAP_ query %u\n", param);
- return 0;
}
val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS, 32);
return MIN2(val, SVGA3D_TEMPREG_MAX);
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
- /*
- * Although PS 3.0 has some addressing abilities it can only represent
- * loops that can be statically determined and unrolled. Given we can
- * only handle a subset of the cases that the state tracker already
- * does it is better to defer loop unrolling to the state tracker.
- */
+ /*
+ * Although PS 3.0 has some addressing abilities it can only represent
+ * loops that can be statically determined and unrolled. Given we can
+ * only handle a subset of the cases that the gallium frontend already
+ * does it is better to defer loop unrolling to the gallium frontend.
+ */
return 0;
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
return 0;
return 0;
case PIPE_SHADER_CAP_SUBROUTINES:
return 0;
+ case PIPE_SHADER_CAP_INT64_ATOMICS:
case PIPE_SHADER_CAP_INTEGERS:
return 0;
+ case PIPE_SHADER_CAP_FP16:
+ case PIPE_SHADER_CAP_FP16_DERIVATIVES:
+ case PIPE_SHADER_CAP_INT16:
+ return 0;
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
return 16;
return 0;
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
+ case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
+ case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
+ case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
return 0;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 32;
return 1;
case PIPE_SHADER_CAP_SUBROUTINES:
return 0;
+ case PIPE_SHADER_CAP_INT64_ATOMICS:
case PIPE_SHADER_CAP_INTEGERS:
return 0;
+ case PIPE_SHADER_CAP_FP16:
+ case PIPE_SHADER_CAP_FP16_DERIVATIVES:
+ case PIPE_SHADER_CAP_INT16:
+ return 0;
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
return 0;
return 0;
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
+ case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
+ case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
+ case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
return 0;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 32;
assert(sws->have_vgpu10);
(void) sws; /* silence unused var warnings in non-debug builds */
- /* Only VS, GS, FS supported */
- if (shader != PIPE_SHADER_VERTEX &&
- shader != PIPE_SHADER_GEOMETRY &&
- shader != PIPE_SHADER_FRAGMENT) {
+ if ((!sws->have_sm5) &&
+ (shader == PIPE_SHADER_TESS_CTRL || shader == PIPE_SHADER_TESS_EVAL))
+ return 0;
+
+ if (shader == PIPE_SHADER_COMPUTE)
return 0;
- }
/* NOTE: we do not query the device for any caps/limits at this time */
return VGPU10_MAX_FS_INPUTS;
else if (shader == PIPE_SHADER_GEOMETRY)
return VGPU10_MAX_GS_INPUTS;
+ else if (shader == PIPE_SHADER_TESS_CTRL)
+ return VGPU11_MAX_HS_INPUT_CONTROL_POINTS;
+ else if (shader == PIPE_SHADER_TESS_EVAL)
+ return VGPU11_MAX_DS_INPUT_CONTROL_POINTS;
else
return VGPU10_MAX_VS_INPUTS;
case PIPE_SHADER_CAP_MAX_OUTPUTS:
return VGPU10_MAX_FS_OUTPUTS;
else if (shader == PIPE_SHADER_GEOMETRY)
return VGPU10_MAX_GS_OUTPUTS;
+ else if (shader == PIPE_SHADER_TESS_CTRL)
+ return VGPU11_MAX_HS_OUTPUTS;
+ else if (shader == PIPE_SHADER_TESS_EVAL)
+ return VGPU11_MAX_DS_OUTPUTS;
else
return VGPU10_MAX_VS_OUTPUTS;
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
case PIPE_SHADER_CAP_SUBROUTINES:
case PIPE_SHADER_CAP_INTEGERS:
return TRUE;
+ case PIPE_SHADER_CAP_FP16:
+ case PIPE_SHADER_CAP_FP16_DERIVATIVES:
+ case PIPE_SHADER_CAP_INT16:
+ return FALSE;
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
return SVGA3D_DX_MAX_SAMPLERS;
case PIPE_SHADER_CAP_PREFERRED_IR:
return PIPE_SHADER_IR_TGSI;
case PIPE_SHADER_CAP_SUPPORTED_IRS:
- return 0;
+ return 0;
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
+ case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
+ case PIPE_SHADER_CAP_INT64_ATOMICS:
+ case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
+ case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
return 0;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 32;
}
-/**
- * Implement pipe_screen::is_format_supported().
- * \param bindings bitmask of PIPE_BIND_x flags
- */
-static boolean
-svga_is_format_supported( struct pipe_screen *screen,
- enum pipe_format format,
- enum pipe_texture_target target,
- unsigned sample_count,
- unsigned bindings)
-{
- struct svga_screen *ss = svga_screen(screen);
- SVGA3dSurfaceFormat svga_format;
- SVGA3dSurfaceFormatCaps caps;
- SVGA3dSurfaceFormatCaps mask;
-
- assert(bindings);
-
- if (sample_count > 1) {
- /* In ms_samples, if bit N is set it means that we support
- * multisample with N+1 samples per pixel.
- */
- if ((ss->ms_samples & (1 << (sample_count - 1))) == 0) {
- return FALSE;
- }
- }
-
- svga_format = svga_translate_format(ss, format, bindings);
- if (svga_format == SVGA3D_FORMAT_INVALID) {
- return FALSE;
- }
-
- /* we don't support sRGB rendering into display targets */
- if (util_format_is_srgb(format) && (bindings & PIPE_BIND_DISPLAY_TARGET)) {
- return FALSE;
- }
-
- /*
- * For VGPU10 vertex formats, skip querying host capabilities
- */
-
- if (ss->sws->have_vgpu10 && (bindings & PIPE_BIND_VERTEX_BUFFER)) {
- SVGA3dSurfaceFormat svga_format;
- unsigned flags;
- svga_translate_vertex_format_vgpu10(format, &svga_format, &flags);
- return svga_format != SVGA3D_FORMAT_INVALID;
- }
-
- /*
- * Override host capabilities, so that we end up with the same
- * visuals for all virtual hardware implementations.
- */
-
- if (bindings & PIPE_BIND_DISPLAY_TARGET) {
- switch (svga_format) {
- case SVGA3D_A8R8G8B8:
- case SVGA3D_X8R8G8B8:
- case SVGA3D_R5G6B5:
- break;
-
- /* VGPU10 formats */
- case SVGA3D_B8G8R8A8_UNORM:
- case SVGA3D_B8G8R8X8_UNORM:
- case SVGA3D_B5G6R5_UNORM:
- break;
-
- /* Often unsupported/problematic. This means we end up with the same
- * visuals for all virtual hardware implementations.
- */
- case SVGA3D_A4R4G4B4:
- case SVGA3D_A1R5G5B5:
- return FALSE;
-
- default:
- return FALSE;
- }
- }
-
- /*
- * Query the host capabilities.
- */
-
- svga_get_format_cap(ss, svga_format, &caps);
-
- if (bindings & PIPE_BIND_RENDER_TARGET) {
- /* Check that the color surface is blendable, unless it's an
- * integer format.
- */
- if (!svga_format_is_integer(svga_format) &&
- (caps.value & SVGA3DFORMAT_OP_NOALPHABLEND)) {
- return FALSE;
- }
- }
-
- mask.value = 0;
- if (bindings & PIPE_BIND_RENDER_TARGET) {
- mask.value |= SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET;
- }
- if (bindings & PIPE_BIND_DEPTH_STENCIL) {
- mask.value |= SVGA3DFORMAT_OP_ZSTENCIL;
- }
- if (bindings & PIPE_BIND_SAMPLER_VIEW) {
- mask.value |= SVGA3DFORMAT_OP_TEXTURE;
- }
-
- if (target == PIPE_TEXTURE_CUBE) {
- mask.value |= SVGA3DFORMAT_OP_CUBETEXTURE;
- }
- else if (target == PIPE_TEXTURE_3D) {
- mask.value |= SVGA3DFORMAT_OP_VOLUMETEXTURE;
- }
-
- return (caps.value & mask.value) == mask.value;
-}
-
-
static void
svga_fence_reference(struct pipe_screen *screen,
struct pipe_fence_handle **ptr,
}
-static boolean
+static bool
svga_fence_finish(struct pipe_screen *screen,
struct pipe_context *ctx,
struct pipe_fence_handle *fence,
uint64_t timeout)
{
struct svga_winsys_screen *sws = svga_screen(screen)->sws;
- boolean retVal;
+ bool retVal;
SVGA_STATS_TIME_PUSH(sws, SVGA_STATS_TIME_FENCEFINISH);
PIPE_DRIVER_QUERY_TYPE_UINT64),
QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED,
PIPE_DRIVER_QUERY_TYPE_BYTES),
+ QUERY("num-command-buffers", SVGA_QUERY_NUM_COMMAND_BUFFERS,
+ PIPE_DRIVER_QUERY_TYPE_UINT64),
QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE,
PIPE_DRIVER_QUERY_TYPE_BYTES),
QUERY("flush-time", SVGA_QUERY_FLUSH_TIME,
PIPE_DRIVER_QUERY_TYPE_UINT64),
QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES,
PIPE_DRIVER_QUERY_TYPE_UINT64),
+ QUERY("num-shader-relocations", SVGA_QUERY_NUM_SHADER_RELOCATIONS,
+ PIPE_DRIVER_QUERY_TYPE_UINT64),
+ QUERY("num-surface-relocations", SVGA_QUERY_NUM_SURFACE_RELOCATIONS,
+ PIPE_DRIVER_QUERY_TYPE_UINT64),
/* running total counters */
QUERY("memory-used", SVGA_QUERY_MEMORY_USED,
PIPE_DRIVER_QUERY_TYPE_UINT64),
QUERY("num-failed-allocations", SVGA_QUERY_NUM_FAILED_ALLOCATIONS,
PIPE_DRIVER_QUERY_TYPE_UINT64),
+ QUERY("num-commands-per-draw", SVGA_QUERY_NUM_COMMANDS_PER_DRAW,
+ PIPE_DRIVER_QUERY_TYPE_FLOAT),
+ QUERY("shader-mem-used", SVGA_QUERY_SHADER_MEM_USED,
+ PIPE_DRIVER_QUERY_TYPE_UINT64),
};
#undef QUERY
static void
init_logging(struct pipe_screen *screen)
{
+ struct svga_screen *svgascreen = svga_screen(screen);
static const char *log_prefix = "Mesa: ";
char host_log[1000];
/* Log Version to Host */
- util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
- "%s%s", log_prefix, svga_get_name(screen));
- svga_host_log(host_log);
+ snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
+ "%s%s\n", log_prefix, svga_get_name(screen));
+ svgascreen->sws->host_log(svgascreen->sws, host_log);
- util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
- "%s%s (%s)", log_prefix, PACKAGE_VERSION, MESA_GIT_SHA1);
- svga_host_log(host_log);
+ snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
+ "%s" PACKAGE_VERSION MESA_GIT_SHA1, log_prefix);
+ svgascreen->sws->host_log(svgascreen->sws, host_log);
/* If the SVGA_EXTRA_LOGGING env var is set, log the process's command
* line (program name and arguments).
if (debug_get_bool_option("SVGA_EXTRA_LOGGING", FALSE)) {
char cmdline[1000];
if (os_get_command_line(cmdline, sizeof(cmdline))) {
- util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
- "%s%s", log_prefix, cmdline);
- svga_host_log(host_log);
+ snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
+ "%s%s\n", log_prefix, cmdline);
+ svgascreen->sws->host_log(svgascreen->sws, host_log);
}
}
}
+/**
+ * no-op logging function to use when SVGA_NO_LOGGING is set.
+ */
+static void
+nop_host_log(struct svga_winsys_screen *sws, const char *message)
+{
+ /* nothing */
+}
+
+
static void
svga_destroy_screen( struct pipe_screen *screen )
{
struct svga_screen *svgascreen = svga_screen(screen);
-
+
svga_screen_cache_cleanup(svgascreen);
mtx_destroy(&svgascreen->swc_mutex);
mtx_destroy(&svgascreen->tex_mutex);
svgascreen->sws->destroy(svgascreen->sws);
-
+
FREE(svgascreen);
}
goto error2;
}
+ debug_printf("%s enabled\n",
+ sws->have_sm5 ? "SM5" :
+ sws->have_sm4_1 ? "SM4_1" :
+ sws->have_vgpu10 ? "VGPU10" : "VGPU9");
+
+ debug_printf("Mesa: %s %s (%s)\n", svga_get_name(screen),
+ PACKAGE_VERSION, MESA_GIT_SHA1);
+
/*
* The D16, D24X8, and D24S8 formats always do an implicit shadow compare
* when sampled from, where as the DF16, DF24, and D24S8_INT do not. So
svgascreen->max_color_buffers = SVGA3D_DX_MAX_RENDER_TARGETS;
/* Multisample samples per pixel */
- if (debug_get_bool_option("SVGA_MSAA", TRUE)) {
- svgascreen->ms_samples =
- get_uint_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES, 0);
+ if (sws->have_sm4_1 && debug_get_bool_option("SVGA_MSAA", TRUE)) {
+ if (get_bool_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_2X, FALSE))
+ svgascreen->ms_samples |= 1 << 1;
+ if (get_bool_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_4X, FALSE))
+ svgascreen->ms_samples |= 1 << 3;
}
- /* We only support 4x, 8x, 16x MSAA */
- svgascreen->ms_samples &= ((1 << (4-1)) |
- (1 << (8-1)) |
- (1 << (16-1)));
+ if (sws->have_sm5 && debug_get_bool_option("SVGA_MSAA", TRUE)) {
+ if (get_bool_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_8X, FALSE))
+ svgascreen->ms_samples |= 1 << 7;
+ }
/* Maximum number of constant buffers */
svgascreen->max_const_buffers =
get_uint_cap(sws, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS, 1);
- assert(svgascreen->max_const_buffers <= SVGA_MAX_CONST_BUFS);
+ svgascreen->max_const_buffers = MIN2(svgascreen->max_const_buffers,
+ SVGA_MAX_CONST_BUFS);
+
+ svgascreen->haveBlendLogicops =
+ get_bool_cap(sws, SVGA3D_DEVCAP_LOGIC_BLENDOPS, FALSE);
+
+ screen->is_format_supported = svga_is_dx_format_supported;
+
+ svgascreen->max_viewports = SVGA3D_DX_MAX_VIEWPORTS;
}
else {
/* VGPU9 */
/* No multisampling */
svgascreen->ms_samples = 0;
+
+ /* Only one viewport */
+ svgascreen->max_viewports = 1;
}
/* common VGPU9 / VGPU10 caps */
svga_screen_cache_init(svgascreen);
- init_logging(screen);
+ if (debug_get_bool_option("SVGA_NO_LOGGING", FALSE) == TRUE) {
+ svgascreen->sws->host_log = nop_host_log;
+ } else {
+ init_logging(screen);
+ }
return screen;
error2:
return NULL;
}
+
struct svga_winsys_screen *
svga_winsys_screen(struct pipe_screen *screen)
{
return svga_screen(screen)->sws;
}
+
#ifdef DEBUG
struct svga_screen *
svga_screen(struct pipe_screen *screen)