svga: reduce unmapping/remapping of the default constant buffer
[mesa.git] / src / gallium / drivers / svga / svga_screen.c
index f6fafca5c0b2a24ef9d07134486aa24123f8f054..ec29ae9f7c651866d2dfd89135124a73518bd0ae 100644 (file)
@@ -86,6 +86,8 @@ svga_get_name( struct pipe_screen *pscreen )
     */
    build = "build: DEBUG;";
    mutex = "mutex: " PIPE_ATOMIC ";";
+#elif defined(VMX86_STATS)
+   build = "build: OPT;";
 #else
    build = "build: RELEASE;";
 #endif
@@ -179,6 +181,7 @@ svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
    switch (param) {
    case PIPE_CAP_NPOT_TEXTURES:
    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
+   case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
       return 1;
    case PIPE_CAP_TWO_SIDED_STENCIL:
       return 1;
@@ -319,6 +322,9 @@ svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_PRIMITIVE_RESTART:
       return 1; /* may be a sw fallback, depending on restart index */
 
+   case PIPE_CAP_GENERATE_MIPMAP:
+      return sws->have_generate_mipmap_cmd;
+
    /* Unsupported features */
    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
@@ -342,6 +348,8 @@ svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
    case PIPE_CAP_DRAW_INDIRECT:
+   case PIPE_CAP_MULTI_DRAW_INDIRECT:
+   case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
    case PIPE_CAP_SAMPLER_VIEW_TARGET:
@@ -349,6 +357,17 @@ svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_VERTEXID_NOBASE:
    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
+   case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
+   case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
+   case PIPE_CAP_INVALIDATE_BUFFER:
+   case PIPE_CAP_STRING_MARKER:
+   case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
+   case PIPE_CAP_QUERY_MEMORY_INFO:
+   case PIPE_CAP_PCI_GROUP:
+   case PIPE_CAP_PCI_BUS:
+   case PIPE_CAP_PCI_DEVICE:
+   case PIPE_CAP_PCI_FUNCTION:
+   case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
       return 0;
    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
       return 64;
@@ -372,6 +391,10 @@ svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_VIDEO_MEMORY:
       /* XXX: Query the host ? */
       return 1;
+   case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
+      return sws->have_vgpu10;
+   case PIPE_CAP_CLEAR_TEXTURE:
+      return sws->have_vgpu10;
    case PIPE_CAP_UMA:
    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
@@ -382,6 +405,18 @@ svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_TGSI_TXQS:
    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
    case PIPE_CAP_SHAREABLE_SHADERS:
+   case PIPE_CAP_DRAW_PARAMETERS:
+   case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
+   case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
+   case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
+   case PIPE_CAP_QUERY_BUFFER_OBJECT:
+   case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
+   case PIPE_CAP_CULL_DISTANCE:
+   case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
+   case PIPE_CAP_TGSI_VOTE:
+   case PIPE_CAP_MAX_WINDOW_RECTANGLES:
+   case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
+   case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
       return 0;
    }
 
@@ -407,6 +442,9 @@ vgpu9_get_shader_param(struct pipe_screen *screen, unsigned shader,
       {
       case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
       case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
+         return get_uint_cap(sws,
+                             SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS,
+                             512);
       case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
       case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
          return 512;
@@ -450,11 +488,15 @@ vgpu9_get_shader_param(struct pipe_screen *screen, unsigned shader,
          return 16;
       case PIPE_SHADER_CAP_PREFERRED_IR:
          return PIPE_SHADER_IR_TGSI;
+      case PIPE_SHADER_CAP_SUPPORTED_IRS:
+         return 0;
       case PIPE_SHADER_CAP_DOUBLES:
       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
+      case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
+      case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
          return 0;
       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
          return 32;
@@ -508,11 +550,15 @@ vgpu9_get_shader_param(struct pipe_screen *screen, unsigned shader,
          return 0;
       case PIPE_SHADER_CAP_PREFERRED_IR:
          return PIPE_SHADER_IR_TGSI;
+      case PIPE_SHADER_CAP_SUPPORTED_IRS:
+         return 0;
       case PIPE_SHADER_CAP_DOUBLES:
       case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
       case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
       case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
       case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
+      case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
+      case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
          return 0;
       case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
          return 32;
@@ -599,11 +645,15 @@ vgpu10_get_shader_param(struct pipe_screen *screen, unsigned shader,
       return SVGA3D_DX_MAX_SAMPLERS;
    case PIPE_SHADER_CAP_PREFERRED_IR:
       return PIPE_SHADER_IR_TGSI;
+   case PIPE_SHADER_CAP_SUPPORTED_IRS:
+         return 0;
    case PIPE_SHADER_CAP_DOUBLES:
    case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
    case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
    case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
    case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
+   case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
+   case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
       return 0;
    case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
       return 32;
@@ -758,18 +808,28 @@ svga_fence_reference(struct pipe_screen *screen,
 
 static boolean
 svga_fence_finish(struct pipe_screen *screen,
+                  struct pipe_context *ctx,
                   struct pipe_fence_handle *fence,
                   uint64_t timeout)
 {
    struct svga_winsys_screen *sws = svga_screen(screen)->sws;
+   boolean retVal;
 
-   if (!timeout)
-      return sws->fence_signalled(sws, fence, 0) == 0;
+   SVGA_STATS_TIME_PUSH(sws, SVGA_STATS_TIME_FENCEFINISH);
 
-   SVGA_DBG(DEBUG_DMA|DEBUG_PERF, "%s fence_ptr %p\n",
-            __FUNCTION__, fence);
+   if (!timeout) {
+      retVal = sws->fence_signalled(sws, fence, 0) == 0;
+   }
+   else {
+      SVGA_DBG(DEBUG_DMA|DEBUG_PERF, "%s fence_ptr %p\n",
+               __FUNCTION__, fence);
+
+      retVal = sws->fence_finish(sws, fence, 0) == 0;
+   }
 
-   return sws->fence_finish(sws, fence, 0) == 0;
+   SVGA_STATS_TIME_POP(sws);
+
+   return retVal;
 }
 
 
@@ -778,29 +838,62 @@ svga_get_driver_query_info(struct pipe_screen *screen,
                            unsigned index,
                            struct pipe_driver_query_info *info)
 {
+#define QUERY(NAME, ENUM, UNITS) \
+   {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
+
    static const struct pipe_driver_query_info queries[] = {
       /* per-frame counters */
-      {"num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS, {0}},
-      {"num-fallbacks", SVGA_QUERY_NUM_FALLBACKS, {0}},
-      {"num-flushes", SVGA_QUERY_NUM_FLUSHES, {0}},
-      {"num-validations", SVGA_QUERY_NUM_VALIDATIONS, {0}},
-      {"map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME, {0},
-       PIPE_DRIVER_QUERY_TYPE_MICROSECONDS},
-      {"num-resources-mapped", SVGA_QUERY_NUM_RESOURCES_MAPPED, {0}},
+      QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS,
+            PIPE_DRIVER_QUERY_TYPE_UINT64),
+      QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS,
+            PIPE_DRIVER_QUERY_TYPE_UINT64),
+      QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES,
+            PIPE_DRIVER_QUERY_TYPE_UINT64),
+      QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS,
+            PIPE_DRIVER_QUERY_TYPE_UINT64),
+      QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME,
+            PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
+      QUERY("num-resources-mapped", SVGA_QUERY_NUM_RESOURCES_MAPPED,
+            PIPE_DRIVER_QUERY_TYPE_UINT64),
+      QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED,
+            PIPE_DRIVER_QUERY_TYPE_BYTES),
+      QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE,
+            PIPE_DRIVER_QUERY_TYPE_BYTES),
+      QUERY("flush-time", SVGA_QUERY_FLUSH_TIME,
+            PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
+      QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES,
+            PIPE_DRIVER_QUERY_TYPE_UINT64),
+      QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS,
+            PIPE_DRIVER_QUERY_TYPE_UINT64),
+      QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES,
+            PIPE_DRIVER_QUERY_TYPE_UINT64),
+      QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS,
+            PIPE_DRIVER_QUERY_TYPE_UINT64),
+      QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES,
+            PIPE_DRIVER_QUERY_TYPE_UINT64),
+      QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES,
+            PIPE_DRIVER_QUERY_TYPE_UINT64),
 
       /* running total counters */
-      {"memory-used", SVGA_QUERY_MEMORY_USED, {0},
-       PIPE_DRIVER_QUERY_TYPE_BYTES},
-      {"num-shaders", SVGA_QUERY_NUM_SHADERS, {0}},
-      {"num-resources", SVGA_QUERY_NUM_RESOURCES, {0}},
-      {"num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS, {0}},
-      {"num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS, {0}},
+      QUERY("memory-used", SVGA_QUERY_MEMORY_USED,
+            PIPE_DRIVER_QUERY_TYPE_BYTES),
+      QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS,
+            PIPE_DRIVER_QUERY_TYPE_UINT64),
+      QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES,
+            PIPE_DRIVER_QUERY_TYPE_UINT64),
+      QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS,
+            PIPE_DRIVER_QUERY_TYPE_UINT64),
+      QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS,
+            PIPE_DRIVER_QUERY_TYPE_UINT64),
+      QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP,
+            PIPE_DRIVER_QUERY_TYPE_UINT64),
    };
+#undef QUERY
 
    if (!info)
-      return Elements(queries);
+      return ARRAY_SIZE(queries);
 
-   if (index >= Elements(queries))
+   if (index >= ARRAY_SIZE(queries))
       return 0;
 
    *info = queries[index];
@@ -932,8 +1025,10 @@ svga_screen_create(struct svga_winsys_screen *sws)
       svgascreen->max_color_buffers = SVGA3D_DX_MAX_RENDER_TARGETS;
 
       /* Multisample samples per pixel */
-      svgascreen->ms_samples =
-         get_uint_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES, 0);
+      if (debug_get_bool_option("SVGA_MSAA", TRUE)) {
+         svgascreen->ms_samples =
+            get_uint_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES, 0);
+      }
 
       /* Maximum number of constant buffers */
       svgascreen->max_const_buffers =
@@ -993,6 +1088,7 @@ svga_screen_create(struct svga_winsys_screen *sws)
                    svgascreen->haveLineStipple, svgascreen->haveLineSmooth,
                    svgascreen->maxLineWidth);
       debug_printf("svga: maxPointSize %g\n", svgascreen->maxPointSize);
+      debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen->ms_samples);
    }
 
    pipe_mutex_init(svgascreen->tex_mutex);